附录
else if(a1==1)
begin out<=0;led<=4'b0100;end else if(a1==0) begin
out<=0;led<=4'b0000; end begin if(reset) begin case(a1)
0:duanxuan<=8'b11111100; 1:duanxuan<=8'b01100000; 2:duanxuan<=8'b11011010; default:duanxuan<=8'b11111111; endcase end end end endmodule
module xiaodou(clk,key_in,key_out)[17]; input clk; input key_in; output key_out; reg[17:0]count_high; reg[17:0]count_low; reg key_reg;
assign key_out=key_reg; always @(posedge clk) begin
if(key_in==1'b0)
count_low<=count_low+1; else
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count_low<=18'd000000; end
always @(posedge clk) begin
if(key_in==1'b1)
count_high<=count_high+1; else
count_high<=18'd00000; end
always @(posedge clk) begin
case(count_high) 18'd51200: key_reg<=1'b1; default:
key_reg<=key_reg; endcase case(count_low) 18'd51200: key_reg<=1'b0; default:
key_reg<=key_reg; endcase end endmodule
附录
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