amplifier which can be configured for use as an on-chip oscillator, as shown in Figure 1. Either a quartz crystal or ceramic resonator may be used. To drive the device from an external clock source, XTAL2 should be left unconnected while XTAL1 is driven as shown in Figure 2. There are no requirements on the duty cycle of the external clock signal, since the input to the internal clocking circuitry is through a
divide-by-two flip-flop, but minimum and maximum voltage high and low time specifications must be observed.
Idle Mode
In idle mode, the CPU puts itself to sleep while all the onchip peripherals remain active. The mode is invoked by software. The content of the on-chip RAM and all the special functions registers remain unchanged during this mode. The idle mode can be terminated by any enabled interrupt or by a hardware reset.
It should be noted that when idle is terminated by a hard ware reset, the device normally resumes program execution, from where it left off, up to two machine cycles before the internal reset algorithm takes control. On-chip hardware inhibits access to internal RAM in this event, but access to the port pins is not inhibited. To eliminate the possibility of an unexpected write to a port pin when Idle is terminated by reset, the instruction following the one that invokes Idle should not be one that writes to a port pin or to external memory.
Status of External Pins During Idle and Power Down Modes mode Program memory ALE ^psen PortPortPortPort0 1 2 3 idle internal 1 data data data Data 1 Idle External 1 1 float Data data Data Power down Internal 0 0 Data Data Data Data Power down External 0 0 float data Data data Power Down Mode In the power down mode the oscillator is stopped, and the instruction that invokes power down is the last instruction executed. The on-chip RAM and Special Function Registers retain their values until the power down mode is terminated. The only exit from power down is a hardware reset. Reset redefines the SFRs but does not change the on-chip RAM. The reset should not be activated before VCC is restored to its normal operating level and must be held active long enough to allow the oscillator to
restart and stabilize.
Program Memory Lock Bits
On the chip are three lock bits which can be left unprogrammed (U) or can be programmed (P) to obtain the additional features listed in the table below:
Lock Bit Protection Modes Program lock bits Protection type Lb1 Lb2 Lb3 1 U U U No program lock features 2 P U U Movc instructions executed from external program memory are disable from fetching code bytes from internal memory, ^ea is sampled and latched on reset, and further programming of the flash disabled 3 P P U Same as mode 2, also verify is disable. 4 P P P Same as mode 3, also external execution is disabled. When lock bit 1 is programmed, the logic level at the EA pin is sampled and latched during reset. If the device is powered up without a reset, the latch initializes to a random value, and holds that value until reset is activated. It is necessary that the latched value of EA be in agreement with the current logic level at that pin in order for the device to function properly. Programming the Flash：
The AT89C51 is normally shipped with the on-chip Flash memory array in the erased state (that is, contents = FFH) and ready to be programmed. The programming interface accepts either a high-voltage (12-volt) or a low-voltage (VCC) program enable signal. The low voltage programming mode provides a convenient way to program the AT89C51 inside the user’s system, while the high-voltage programming mode is compatible with conventional third party Flash or EPROM programmers.
The AT89C51 is shipped with either the high-voltage or low-voltage
programming mode enabled. The respective top-side marking and device signature codes are listed in the following table. Vpp=12v Vpp=5v Top-side mark AT89C51 AT89C51 xxxx xxxx-5 yyww yyww signature (030H)=1EH (030H)=1EH (031H)=51H (031H)=51H (032H)=FFH (032H)=05H The AT89C51 code memory array is programmed byte-bybyte in either programming mode. To program any nonblank byte in the on-chip Flash
Programmable and Erasable Read Only Memory, the entire memory must be erased using the Chip Erase Mode. Programming Algorithm:
Before programming the AT89C51, the address, data and control signals should be set up according to the Flash programming mode table and Figures 3 and 4. To program the AT89C51, take the following steps.
1. Input the desired memory location on the address lines. 2. Input the appropriate data byte on the data lines. 3. Activate the correct combination of control signals.
4. Raise EA/VPP to 12V for the high-voltage programming mode.
5. Pulse ALE/PROG once to program a byte in the Flash array or the lock bits. The byte-write cycle is self-timed and typically takes no more than 1.5 ms. Repeat steps 1 through 5, changing the address and data for the entire array or until the end of the object file is reached.
Data Polling: The AT89C51 features Data Polling to indicate the end of a write cycle. During a write cycle, an attempted read of the last byte written will result in the complement of the written datum on PO.7. Once the write cycle has been completed, true data are valid on all outputs, and the next cycle may begin. Data Polling may begin any time after a write cycle has been initiated.
Ready/Busy: The progress of byte programming can also be monitored by the RDY/BSY output signal. P3.4 is pulled low after ALE goes high during programming to indicate BUSY. P3.4 is pulled high again when programming is done to indicate READY.
Program Verify: If lock bits LB1 and LB2 have not been programmed, the
programmed code data can be read back via the address and data lines for verification. The lock bits cannot be verified directly. Verification of the lock bits is achieved by observing that their features are enabled.
Chip Erase: The entire Flash Programmable and Erasable Read Only Memory array is erased electrically by using the proper combination of control signals and by holding ALE/PROG low for 10 ms. The code array is written with all “1”s. The chip erase operation must be executed before the code memory can be re-programmed.
Reading the Signature Bytes: The signature bytes are read by the same
procedure as a normal verification of locations 030H, 031H, and 032H, except that P3.6 and P3.7 must be pulled to a logic low. The values returned are as follows.
(030H) = 1EH indicates manufactured by Atmel (031H) = 51H indicates 89C51
(032H) = FFH indicates 12V programming (032H) = 05H indicates 5V programming Programming Interface
Every code byte in the Flash array can be written and the entire array can be erased by using the appropriate combination of control signals. The write operation cycle is selftimed and once initiated, will automatically time itself to completion.
mode Write code data Read code data RST H H ^PSEN ALE/^PROG L L L H H H/12V L H L H H H H H Bit-1 H ^EA/Vpp H/12V P2.6 P2.7 P3.6 P3.7 L H H H Write lock Bit-2 H Bit-3 H L L L L H H/12V H/12V H H H L L L L H L L L L L H/12V H H L L Chip erase Read signature syte H H Table 1 Flash Programming Modes Note: 1.chip erase requires a 10-ms PROG pulse
Figure 3. Programming the Flash Figure 4. Verifying the Flash
Flash Programming and Verification Characteristics
TA = 0°C to 70°C, VCC = 5.0 ??10% Symbol parameter min 11.5 Vpp⑴ Programming enable voltage Ipp⑴ Programming enable current 1/Tclcl Oscillator frequency 3 Tavgl Address setup to 48Tclcl ^PSEN low Tghax Address hole after 48Tclcl ^PSEN Tdvgl Data setup to ^PSEN 48Tclcl low Tghdx Data hole after ^PSEN 48Tclcl Tehsh P2.7(^enable)high to 48Tclcl
max 12.5 1.0 24 Units V mA MHZ Vpp Tshgl Vpp setup to ^PSEN 10 us low 10 us Tghsl⑴ Vpp hole after ^PSEN Tglgh ^PSEN width 1 110 us Tavqv Address to data valid 48Tclcl Telqv ^enable low to data 48Tclcl valid Tehqz Data float after 0 48Tclcl ^enable Tghbl ^PSEN high to ^busy 1.0 us low Twc Byte write cycle time 2.0 ms Note: 1. Only used in 12-volt programming mode. Flash Programming and Verification Waveforms - High Voltage Mode (VPP = 12V)
Flash Programming and Verification Waveforms - Low Voltage Mode (VPP = 5V)