弄了好长时间vhdl，一直对testbench很迷惑。前几天静下心来好好看了下资料，终于会写简单的testbench了。 六进制计数器的代码
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1. library ieee;
2. use ieee.std_logic_1164.all; 3. use ieee.std_logic_arith.all; 4. --use ieee.std_logic_unsigned.all; 5.
6. entity cnt6 is 7. port
8. (clr,en,clk :in std_logic;
9. q :out std_logic_vector(2 downto 0) 10. ); 11. end entity; 12.
13. architecture rtl of cnt6 is
14. signal tmp :std_logic_vector(2 downto 0); 15. begin
16. process(clk)
17. -- variable q6:integer; 18. begin
19. if(clk'event and clk='1') then 20. if(clr='0')then 21. tmp<=\; 22. elsif(en='1') then 23. if(tmp=\)then 24. tmp<=\; 25. else
26. tmp<=unsigned(tmp)+'1'; 27. end if; 28. end if; 29. end if; 30. q<=tmp; 31. -- qa<=q(0); 32. -- qb<=q(1); 33. -- qc<=q(2); 34. end process; 35. end rtl;
六进制计数器testbench的代码
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1. library ieee;
2. use ieee.std_logic_1164.all; 3.
4. entity cnt6_tb is 5. end cnt6_tb; 6.
7. architecture rtl of cnt6_tb is 8. component cnt6 9. port(
10. clr,en,clk :in std_logic;
11. q :out std_logic_vector(2 downto 0) 12. );
13. end component; 14.
15. signal clr :std_logic:='0'; 16. signal en :std_logic:='0'; 17. signal clk :std_logic:='0';
18. signal q :std_logic_vector(2 downto 0); 19.
20. constant clk_period :time :=20 ns; 21. begin
22. instant:cnt6 port map 23. (
24. clk=>clk,en=>en,clr=>clr,q=>q 25. );
26. clk_gen:process 27. begin
28. wait for clk_period/2; 29. clk<='1';
30. wait for clk_period/2; 31. clk<='0'; 32. end process; 33.
34. clr_gen:process 35. begin 36. clr<='0'; 37. wait for 30 ns; 38. clr<='1'; 39. wait; 40. end process;
41.
42. en_gen:process 43. begin 44. en<='0'; 45. wait for 50ns; 46. en<='1'; 47. wait; 48. end process; 49. end rtl;
其实testbench也有自己固定的一套格式，总结如下：
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1. --测试平台文件(testbench)的基本结构 2. library ieee;
3. use ieee.std_logic_1164.all; 4.
5. entity test_bench is --测试平台文件的空实体（不需要端口定义) 6.
7. end test_bench; 8.
9. architecture tb_behavior of test_bench is 10.
11. component entity_under_test --被测试元件的声明 12. port(
13. list-of-ports-theri-types-and-modes 14. );
15. end component; 16. 17. begin
18. instantiation:entity_under_test port map 19. (
20. port-associations 21. ); 22.
23. process() --产生时钟信号 24. ……
25. end process; 26.
27. process() --产生激励源 28. ……
29. end process; 30. end tb_behavior; 31.
32. ------------------------------------------------------------------- 33. --简单计数程序源码 34. library ieee;
35. use ieee.std_logic_1164.all; 36. use ieee.std_logic_unsigned.all; 37. use ieee.std_logic_unsigned.all; 38.
39. entity sim_counter is 40. port(
41. clk :in std_logic; 42. reset :in std_logic;
43. count :out std_logic_vector(3 downto 0) 44. ); 45. end entity; 46.
47. architecture behavioral of sim_counter is 48.
49. signal temp :std_logic_vector(3 downto 0); 50. 51. begin
52. process(clk,reset) 53. begin
54. if reset='1' then 55. temp<=\;
56. elsif clk'event and clk='1' then 57. temp<=temp+1; 58. end if; 59. end process; 60. count<=temp; 61. end behavioral; 62.
63. ------------------------------------------------------------------- 64. --简单计数程序，测试文件代码(testbench) 65. library ieee;
66. use ieee.std_logic_1164.all; 67. use ieee.std_logic_unsigned.all; 68. use ieee.numeric_std.all; 69.
70. entity counter_tb_vhd is --测试平台实体 71. end counter_tb_vhd; 72.
73. architecture behavior of counter_tb_vhd is 74. --被测试元件（DUT）的声明 75. component sim_counter 76. port(
77. clk :in std_logic; 78. reset :in std_logic;
79. count :out std_logic_vector(3 downto 0) 80. );
81. end component; 82. --输入信号
83. signal clk:std_logic:='0'; 84. signal reset :std_logic:='0'; 85. --输出信号
86. signal count :std_logic_vector(3 downto 0); 87.
88. constant clk_period :time :=20 ns; --时钟周期的定义 89. 90. begin
91. dut:sim_counter port map(
92. clk=>clk,reset=>reset,counter=>counter 93. );
94. clk_gen:process 95. begin 96. clk='1';
97. wait for clk_period/2; 98. clk='0';
99. wait for clk_period/2; 100. end process; 101.
102. tb:process --激励信号 103. begin
104. wait for 20 ns; 105. reset<='1'; 106. wait for 20 ns; 107. reset<='0'; 108. wait for 200 ns;
109. wait; --will wait forever; 110. end process; 111. end; 112. 113.
114. --激励信号的产生方式
115. --1.以一定的离散时间间隔产生激励信号的波形
116. --2.基于实体的状态产生激励信号，也就是说基于实体的输出响应产生激励信号