图4 显示“96”仿真图
4 心得体会
通过这次的课程设计让我对VHDL语言以及电路设计的理论有了更加深入的了解，课程设计是培养学生综合运用所学知识,发现、提出、分析和解决实际问题,锻炼实践能力的重要环节，这次课程设计虽然很累，但我学到了不少东西，对软件的设计过程和方法有了更深入的了解。在课程设计过程中，我学到了很多人生的哲理，懂得怎么样去制定计划，怎么样去实现这个计划，并掌握了在执行过程中怎么样去克服心理上的不良情绪，黑夜过去了，我们收获的是黎明。在本次实践中，给我印象最为深刻的是在文件删除程序的编译过程中，先有我的各个子程序都已经编辑成功，那么这最后的程序就将是我成功的关键。
这次课程设计顺利完成了，在设计中遇到了很多问题，最后都是经过查阅相关的资料和在同学的帮助下，终于游逆而解。同时，在我学得到很多实用的知识，同时，对给过我帮助的所有同学再次表示忠心的感谢！
参考文献
【1】黄继业.EDA技术使用教程[M].北京:科学出版社，2010
【2】王云亮.电力电子技术[M].北京：电子工业出版社，2009 【3】康光华.电子技术基础[M].北京:高等教育出版社，2006
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附录1
library ieee;
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use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; use ieee.std_logic_arith.all; entity look is
port(d:in std_logic_vector(26 downto 0); clk3:in std_logic;
led7s1,led7s2,led7s3,led7s4,led7s5,led7s6,led7s7,led7s8:out std_logic_vector(6 downto 0)); end;
architecture one of look is
signal ai,bi,ci,ki,ei,fi,gi,hi:integer range 0 to 9; signal di:integer range 0 to 99999999; begin
di<=conv_integer(d); process(di)
variable a,b,c,k,e,f,g,h:integer range 0 to 9; begin a:=di rem 10; b:=(di-a) rem 100; c:=(di-a-10*b) rem 1000; k:=(di-a-10*b-c*100) rem 10000;
e:=(di-a-10*b-c*100-k*1000) rem 100000;
f:=(di-a-10*b-c*100-k*1000-10000*e) rem 1000000;
g:=(di-a-10*b-c*100-k*1000-10000*e-100000*f) rem 10000000;
h:=(di-a-10*b-c*100-k*1000-10000*e-100000*f-1000000*g)/10000000;ai<=a; bi<=b; ci<=c; ki<=k; ei<=e; fi<=f; gi<=g; hi<=h; end process; process(ai) begin case ai is
when 0=>led7s1(6 downto 0)<=\ when 1=>led7s1(6 downto 0)<=\
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when 2=>led7s1(6 downto 0)<=\ when 3=>led7s1(6 downto 0)<=\ when 4=>led7s1(6 downto 0)<=\ when 5=>led7s1(6 downto 0)<=\ when 6=>led7s1(6 downto 0)<=\ when 7=>led7s1(6 downto 0)<=\ when 8=>led7s1(6 downto 0)<=\ when 9=>led7s1(6 downto 0)<=\ when others=>led7s1(6 downto 0)<=\end case; end process; process(bi) begin case bi is
when 0=>led7s2(6 downto 0)<=\ when 1=>led7s2(6 downto 0)<=\ when 2=>led7s2(6 downto 0)<=\ when 3=>led7s2(6 downto 0)<=\ when 4=>led7s2(6 downto 0)<=\ when 5=>led7s2(6 downto 0)<=\ when 6=>led7s2(6 downto 0)<=\ when 7=>led7s2(6 downto 0)<=\ when 8=>led7s2(6 downto 0)<=\ when 9=>led7s2(6 downto 0)<=\ when others=>led7s2(6 downto 0)<=\end case; end process; process(ci) begin case ci is
when 0=>led7s3(6 downto 0)<=\ when 1=>led7s3(6 downto 0)<=\ when 2=>led7s3(6 downto 0)<=\ when 3=>led7s3(6 downto 0)<=\ when 4=>led7s3(6 downto 0)<=\ when 5=>led7s3(6 downto 0)<=\ when 6=>led7s3(6 downto 0)<=\
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when 7=>led7s3(6 downto 0)<=\ when 8=>led7s3(6 downto 0)<=\ when 9=>led7s3(6 downto 0)<=\ when others=>led7s3(6 downto 0)<=\end case; end process; process(ki) begin case ki is
when 0=>led7s4(6 downto 0)<=\ when 1=>led7s4(6 downto 0)<=\ when 2=>led7s4(6 downto 0)<=\ when 3=>led7s4(6 downto 0)<=\ when 4=>led7s4(6 downto 0)<=\ when 5=>led7s4(6 downto 0)<=\ when 6=>led7s4(6 downto 0)<=\ when 7=>led7s4(6 downto 0)<=\ when 8=>led7s4(6 downto 0)<=\ when 9=>led7s4(6 downto 0)<=\ when others=>led7s4(6 downto 0)<=\end case; end process; process(ei) begin case ei is
when 0=>led7s5(6 downto 0)<=\ when 1=>led7s5(6 downto 0)<=\ when 2=>led7s5(6 downto 0)<=\ when 3=>led7s5(6 downto 0)<=\ when 4=>led7s5(6 downto 0)<=\ when 5=>led7s5(6 downto 0)<=\ when 6=>led7s5(6 downto 0)<=\ when 7=>led7s5(6 downto 0)<=\ when 8=>led7s5(6 downto 0)<=\ when 9=>led7s5(6 downto 0)<=\ when others=>led7s5(6 downto 0)<=\end case;
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