2、触发器
ENTITY regdff IS PORT --实体说明，定义输入和输出端口
( d, clk :IN BIT; q :OUT BIT );
END regdff;
------------边沿触发器第一种实现------------------------------------------------------------------------- ARCHITECTURE a1 OF regdff IS BEGIN PROCESS (clk) --时钟脉冲触发 BEGIN IF (clk'EVENT AND clk = '1') THEN --定义上升沿触发 q <= d; --特性方程，也可以直接通过算法实现 END IF; END PROCESS; END a1;
第二种实现------------------------------------------------------------------------------------- ARCHITECTURE a2 OF regdff IS BEGIN PROCESS --没有敏感信号表有，但内部WAIT语句 BEGIN WAIT UNTIL (clk'EVENT AND clk = '1'); --定义上升沿触发 q <= d; END PROCESS; END a2;