A 201.4 GOPS real-time multi-object recognitionprocessor is presented with a three-stage pipelined architecture.Visual perception based multi-object recognition algorithm isapplied to give multiple attentions to multiple objects in the inputimage. For human-like multi-object perception, a neural perceptionengine is proposed with biologically inspired neural networksand fuzzy logic circ
40IEEEJOURNALOFSOLID-STATECIRCUITS,VOL.45,NO.1,JANUARY
2010
Fig.10.Blockdiagramofdecisionprocessor.
V.MULTI-CASTINGNETWORK-ON-CHIP
AsthenumberofIPblocksincreasestoaddresscomputingrequirementsofrecentmultimediaprocessing,conventionalsharedmediumbasedcommunicationrevealsitslimitationstohandlesimultaneousdatatransactionsamongmultipleIPblocks.Asanalternative,anetwork-on-chip(NoC)ishigh-lightedassuitablecommunicationarchitectureinmulti-coreerainspiteofitshighimplementationcostscomparedwithconventionalbus,becauseitprovidessuf cientbandwidthtomultipleIPblocksandhasgoodscalabilitywithdistributedrouterswitches[15]–[17].Inthisprocessor,amulti-castingnetwork-on-chip(MC-NoC)isproposedtointegrateallof21IPblocks.Tocopewiththeprocessor’sapplication-drivendatatransactionssuchas1-to-Nbroad/multi-castingandinter-pro-cessordatacommunications,theMC-NoChasanewcombinedarchitectureandsupportsamulti-castingcapability.
Fig.11showstheproposedMC-NoCarchitecturethatcon-sistsofa
910systemnetworkandfour
77SPUcluster(SPC)networks.The16SPUsareconnectedtothesystemnetworkthroughthefourSPCnetworkswhiletheNPE,STM,DP,andtwoexternalinterfacesaredirectlyconnectedtothesystemnetwork.Itadoptsahierarchicalstartopology[15]asabasictopologyforlowlatencydatacommunications,andthen,supplementsaringtopologytotheSPCnetworksforhigh-speedinter-SPUdatatransactions.Theadditionalnetworklinksforthecombinedtopologyprovides25.6GB/saggregatedbandwidthbetweentheSPCnetworksandallowseachSPUtoaccesstheotherSPUsinneighborclustersintwoswitchhops.Inoverall,topology-combinedMC-NoCprovidesa118.4GB/stotalbandwidthwiththeswitchhoplatencyoflessthan3.TheproposedMC-NoCadoptsawormholeroutingprotocolwhosepacketiscomposedofheader,address,anddata owcontrolunits(FLITs).EachFLITconsistsof2-bitcontrolsignalsand34-bitdatasignalsincluding2-bitFLITtypeindicator.TheheaderFLITcontainsallinformationfortheentirepackettransmissionsuchas4-bitburstlengthforburstdata
transaction
Fig.11.Proposedmulti-castingNoCarchitecture.
uptoeightFLITsand2-bitprioritylevelforquality-of-service.The16-bitsourcede nedroutinginformation(RI)allowsfourswitchtraversalsfornormalpacketsandmulti-castingtoarbi-trarySPUsformulti-castingpackets.Incaseofmulti-castingpackets,eachbitof16-bitRIindicateseachdestinationSPU.IntheMC-NoC,multi-castingfromtheNPE/STMtothe16SPUsissupportedtoaccelerate1-to-Ndatatransactionssuchasprogramkerneldistributionandimagedatadownload.Tothisend,eachnetworkswitchisdesignedtohavemulti-castingability.Fig.12showsafour-stagepipelinedmulti-castingcrossbarswitchanditsmulti-castingport.Itconsistsofinputports,arbiters,muxbasedcrossbarfabric,andoutputports.At rst,theincomingFLITsarebufferedatthe8-depthFIFOqueuethatcontainsthesynchronizationinterface[18]forheterogeneousclockdomainconversion.Then,eachactiveinputportsendsarequestsignaltoitsdestinationarbitertogetagrantsignaltotraversethecrossbarfabric.Forschedulingofgrantsignals,thearbitersperformasimpleround-robinsched-ulingaccordingtotheprioritylevels.Incaseofmulti-casting