--------------------------------分频模块-------------------------------library ieee;------分频器 use ieee.std_logic_11
64.all; use ieee.std_logic_unsigned.all; entity fenpin is port(clk:in std_logic; clk1k,clk100,clk1:out std_logic); end fenpin; architecture a of fenpin is signal count:integer range 0 to 999; signal count1:integer range 0 to 9; signal count2:integer range 0 to 99; signal m,n:std_logic; begin p1: process(clk) ---------1kHz 分频 begin if(clk'event and clk='1')then if(count=999) then count<=0; else count<=count+1; end if; if(count<499) then m<='1'; else m<='0'; end if; end if; end process;
数码管选通输出使用
p2:process(m) -------------100Hz 分频 begin if(m'event and m='1') then if(count1=9)then count1<=0; else count1<=count1+1; end if; if(count1<4)then n<='1'; else n<='0'; end if; end if; end process;
扩展功能使用 m 来驱动
p3:process(n) ----------------1Hz 分频
倒计时使用
n 来驱动