通信工程eda实验报告
ARCHITECTURE ONE OF VHDL42 IS
SIGNAL C:STD_LOGIC_VECTOR(2 DOWNTO 0); BEGIN
P1:PROCESS(CLK) BEGIN
IF CLK'EVENT AND CLK='1'THEN IF C<"111"THEN C<=C+1;ELSE C<="000"; END IF; END IF; S<=C;
END PROCESS P1; P2:PROCESS(D) BEGIN CASE D IS
WHEN "0000"=> A<="0111111";WHEN "0001"=> A<="0000110"; WHEN "0010"=> A<="1011011";WHEN "0011"=> A<="1001111"; WHEN "0100"=> A<="1100110";WHEN "0101"=> A<="1101101"; WHEN "0110"=> A<="1111101";WHEN "0111"=> A<="0000111"; WHEN "1000"=> A<="1111111";WHEN "1001"=> A<="1101111"; WHEN "1010"=> A<="1110111";WHEN "1011"=> A<="1111100"; WHEN "1100"=> A<="0111001";WHEN "1101"=> A<="1011110"; WHEN "1110"=> A<="1111001";WHEN "1111"=> A<="1110001"; WHEN OTHERS=> NULL; END CASE; END PROCESS P2; END;
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