元器件交易网
AT24C164
Figure 2. Bus Timing
SCL: Serial Clock, SDA: Serial Data I/O
Figure 3. Write Cycle Timing
SCL: Serial Clock, SDA: Serial Data I/O
Note:
1.The write cycle time tWR is the time from a valid stop condition of a write sequence to the end of the internal clear/write cycle.
Figure 4.
Data Validity
7
0105J–SEEPR–12/06