河南理工大学毕业设计（论文）说明书
To facilitate accessing both internal and external data memory, two banks of 16-bit Data Pointer Registers are provided: DPO at SFR address locations 82H-83H and DP1 at 84H-85H.Bit DPS=0 in SFR AUXR1 selects DPO and DPS=1 selects DP1. The user should ALWAYS initialize the DPS bit to the appropriate value before accessing the respective Data Pointer Register.
Power Off Flag:
The Power Off Flag (POF) is located at bit 4 (PCON.4) in the PCON SFR. POF is set to \affected by reset.
Memory Organization：
MCS-51 devices have a separate address space for Program and Data Memory. Up to 64K bytes each of external Program and Data Memory can be addressed.
Program Memory：
If the EA pin is connected to GND, all program fetches are directed to external memory. On the AT89S51，if EA is connected to Vcc, program fetches to addresses OOOOH through FFFH are directed to internal memory and fetches to addresses 1000H through FFFFH are directed to external memory.
Data Memory：
The AT89S51 implements 128 bytes of on-chip RAM. The 128 bytes are accessible via direct and indirect addressing modes. Stack operations are examples of indirect addressing, so the 128 bytes of data RAM are available as stack space.
Watchdog Timer (One-time Enabled with Reset-out)：
The WDT is intended as a recovery method in situations where the CPU may be subjected to software upsets. The WDT consists of a 14-bit counter and the Watchdog Timer Reset (WDTRST) SFR. The WDT is defaulted to disable from exiting reset. To enable the WDT, a user must write 01 EH and OE1 H in sequence to the WDTRST register (SFR location OA6H). When the WDT is enabled, it will increment every machine cycle while the oscillator is running. The WDT timeout
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河南理工大学毕业设计（论文）说明书
period is dependent on the external clock frequency. There is no way to disable the WDT except through reset (either hardware reset or WDT overflow reset). When WDT overflows, it will drive an output RESET HIGH pulse at the RST pin.
The use of watchdog (WDT):
WDT to be open to write 01EH and 0E1H in sequence to WDTRST registers (SFR's address 0A6H), when the WDT opened, take some time to 01EH and 0E1H to WDTRST count register in order to avoid WDT overflow. WDT counter 14 count reached 16383 (3FFFH), WDT will overflow and reset the device. WDT is turned on, it will be with the crystal oscillator in each machine cycle count, which means that users must be less than 16,383 machines each cycle reset WDT, that is to write 01EH and 0E1H to WDTRST register, WDTRST write only register.WDT counter can not be read neither write, when the WDT overflows, it is usually RST pin will reset the output of high pulse. Reset pulse duration for the 98 × Tosc, and Tosc = 1/Fosc (crystal oscillation frequency).
In order to optimize the work WDT must be at the right time code WDT reset periodically to prevent the WDT overflow.
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