FCTL3 = FWKEY; // Clear Lock bit
*Flash_ptrB = 0; // Dummy write to erase Flash segment B FCTL1 = FWKEY + WRT; // Set WRT bit for write operation
for (i=0; i<128; i++) {
DataBuffer[i] = *Flash_ptrA++;
*Flash_ptrB++ = DataBuffer[i]; // Copy value segment A to segment B }
FCTL1 = FWKEY; // Clear WRT bit FCTL3 = FWKEY + LOCK; // Set LOCK bit } //****************************************************************************** // MSP-FET430P140 Demo - USART0, Ultra-Low Pwr UART 2400 Echo ISR, 32kHz ACLK //
// Description: Echo a received character, RX ISR used. In the Mainloop UART0 // is made ready to receive one character with interrupt active. The Mainloop // waits in LPM3. The UART0 ISR forces the Mainloop to exit LPM3 after // receiving one character which echo's back the received character.
// ACLK = UCLK0 = LFXT1 = 32768, MCLK = SMCLK = DCO~ 800k
// Baud rate divider with 32768hz XTAL @2400 = 32768Hz/2400 = 13.65 (000Dh) // //* An external watch crystal is required on XIN XOUT for ACLK *// //
// MSP430F149 // -----------------
// /|\\| XIN|-
// | | | 32kHz // --|RST XOUT|- // | |
// | P3.4|-----------> // | | 2400 - 8N1 // | P3.5|<----------- //
//
// M. Buccini
// Texas Instruments Inc.
// Feb 2005
// Built with IAR Embedded Workbench Version: 3.21A
//******************************************************************************
#include
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void main(void)
{
BoardConfig(0xb8);
WDTCTL = WDTPW + WDTHOLD; // Stop WDT
P3SEL |= 0x30; // P3.4,5 = USART0 TXD/RXD ME1 |= UTXE0 + URXE0; // Enable USART0 TXD/RXD UCTL0 |= CHAR; // 8-bit character UTCTL0 |= SSEL0; // UCLK = ACLK UBR00 = 0x0D; // 32k/2400 - 13.65 UBR10 = 0x00; //
UMCTL0 = 0x6B; // Modulation
UCTL0 &= ~SWRST; // Initialize USART state machine IE1 |= URXIE0; // Enable USART0 RX interrupt
// Mainloop for (;;)
{
_BIS_SR(LPM3_bits + GIE); // Enter LPM3 w/interrupt while (!(IFG1 & UTXIFG0)); // USART0 TX buffer ready? TXBUF0 = RXBUF0; // RXBUF0 to TXBUF0 }
}
// UART0 RX ISR will for exit from LPM3 in Mainloop #pragma vector=UART0RX_VECTOR __interrupt void usart0_rx (void) {
_BIC_SR_IRQ(LPM3_bits); // Clear LPM3 bits from 0(SR) }
//****************************************************************************** // MSP-FET430P140 Demo - USART0, Ultra-Low Pwr UART 9600 Echo ISR, 32kHz ACLK //
// Description: Echo a received character, RX ISR used. In the Mainloop UART0 // is made ready to receive one character with interrupt active. The Mainloop // waits in LPM3. The UART0 ISR forces the Mainloop to exit LPM3 after // receiving one character which echo's back the received character.
// ACLK = UCLK0 = LFXT1 = 32768, MCLK = SMCLK = DCO~ 800k
// Baud rate divider with 32768hz XTAL @9600 = 32768Hz/9600 = 3.41 (0003h 4Ah ) // //* An external watch crystal is required on XIN XOUT for ACLK *// //
// MSP430F149 // -----------------
// /|\\| XIN|- // | | | 32kHz // --|RST XOUT|-
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// | |
// | P3.4|-----------> // | | 9600 - 8N1 // | P3.5|<----------- // //
// M. Buccini
// Texas Instruments Inc. // Feb 2005
// Built with IAR Embedded Workbench Version: 3.21A
//******************************************************************************
#include
void main(void) {
BoardConfig(0xb8);
WDTCTL = WDTPW + WDTHOLD; // Stop WDT
P3SEL |= 0x30; // P3.4,5 = USART0 TXD/RXD
ME1 |= UTXE0 + URXE0; // Enable USART0 TXD/RXD UCTL0 |= CHAR; // 8-bit character UTCTL0 |= SSEL0; // UCLK = ACLK UBR00 = 0x03; // 32k/9600 - 3.41
UBR10 = 0x00; //
UMCTL0 = 0x4A; // Modulation
UCTL0 &= ~SWRST; // Initialize USART state machine IE1 |= URXIE0; // Enable USART0 RX interrupt
// Mainloop for (;;)
{
_BIS_SR(LPM3_bits + GIE); // Enter LPM3 w/interrupt while (!(IFG1 & UTXIFG0)); // USART0 TX buffer ready? TXBUF0 = RXBUF0; // RXBUF0 to TXBUF0 } }
// UART0 RX ISR will for exit from LPM3 in Mainloop #pragma vector=UART0RX_VECTOR
__interrupt void usart0_rx (void) {
_BIC_SR_IRQ(LPM3_bits); // Clear LPM3 bits from 0(SR) }
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//****************************************************************************** // MSP-FET430P140 Demo - USART0, UART 19200 Echo ISR, XT2 HF XTAL ACLK //
// Description: Echo a received character, RX ISR used. Normal mode is LPM0, // USART0 RX interrupt triggers TX Echo. Though not required, MCLK = XT2. // ACLK = n/a, MCLK = SMCLK = UCLK0 = XT2 = 8MHz
// Baud rate divider with 8Mhz XTAL @19200 = 8MHz/19200 = 416.66 ~ 417 (01A0h) // //* An external 8MHz XTAL on X2IN X2OUT is required for XT2CLK *// // //* Min Vcc required varies with MCLK frequency - refer to datasheet *//
//
//
// MSP430F149 // -----------------
// /|\\| XT2IN|- // | | | 8Mhz // --|RST XT2OUT|-
// | |
// | P3.4|------------> // | | 19200 - 8N1 // | P3.5|<------------ //
//
// M. Buccini
// Texas Instruments Inc. // Feb 2005
// Built with IAR Embedded Workbench Version: 3.21A
//******************************************************************************
#include
void main(void) {
volatile unsigned int i;
BoardConfig(0xb8);
P3SEL |= 0x30; // P3.4,5 = USART0 TXD/RXD WDTCTL = WDTPW + WDTHOLD; // Stop WDT
BCSCTL1 &= ~XT2OFF; // XT2on do {
IFG1 &= ~OFIFG; // Clear OSCFault flag
for (i = 0xFF; i > 0; i--); // Time for flag to set
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}
while ((IFG1 & OFIFG)); // OSCFault flag still set?
BCSCTL2 |= SELM_2 + SELS; // MCLK = SMCLK = XT2 (safe)
ME1 |= UTXE0 + URXE0; // Enable USART0 TXD/RXD UCTL0 |= CHAR; // 8-bit character UTCTL0 |= SSEL1; // UCLK = SMCLK UBR00 = 0xA0; // 8Mhz/19200 ~ 417 UBR10 = 0x01; //
UMCTL0 = 0x00; // no modulation
UCTL0 &= ~SWRST; // Initialize USART state machine IE1 |= URXIE0; // Enable USART0 RX interrupt
_BIS_SR(LPM0_bits + GIE); // Enter LPM0 w/ interrupt }
#pragma vector=UART0RX_VECTOR __interrupt void usart0_rx (void) {
while (!(IFG1 & UTXIFG0)); // USART0 TX buffer ready? TXBUF0 = RXBUF0; // RXBUF0 to TXBUF0 } //****************************************************************************** // MSP-FET430P140 Demo - USART0, UART 115200 Echo ISR, XT2 HF XTAL ACLK //
// Description: Echo a received character, RX ISR used. Normal mode is LPM0, // USART0 RX interrupt triggers TX Echo. Though not required, MCLK= XT2. // // // // // //
// MSP430F149 // -----------------
// /|\\| XT2IN|- // | | | 8Mhz // --|RST XT2OUT|- // | |
// | P3.4|------------> // | | 115200 - 8N1 // | P3.5|<------------ // //
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ACLK = n/a, MCLK = SMCLK = UCLK0 = XT2 = 8MHz
Baud rate divider with 8Mhz XTAL = 8000000/115200 = 0069 (0045h) //* An external 8MHz XTAL on X2IN X2OUT is required for XT2CLK *// //* Min Vcc required varies with MCLK frequency - refer to datasheet *//