3、在 1 24、在 1件
2 3 4 5
Quartus II中建立一个蜂鸣器 ） 用VHDL语言编写蜂鸣器程序
） 编译成功后Creat symbol，生成Project sing
Quartus II中编译Nios II硬件系统并生成配置文件 ） 在Quartus II加入Nios II系统符号到顶层文） 给各端口加入输入输出引脚，并重命名 ） 设置参数 ） 编译顶层文件 ） 分配管脚
6） 再次编译
5、在Nios II IDE中建立C/C++工程，编写用户程序 6、编译用户程序
7、下载.SOF至FPGA,运行程序，观察结果
五、设计程序
蜂鸣器程序（VHDL）:
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL; ENTITY sing1 IS PORT(
CLK:IN STD_LOGIC; p:IN STD_LOGIC;
-- DIGIT:BUFFER STD_LOGIC_VECTOR(6 DOWNTO 0); SPEAKER:OUT STD_LOGIC);
END ENTITY;
ARCHITECTURE SONG OF sing1 IS
SIGNAL DRIVER,ORIGIN:STD_LOGIC_VECTOR(12 DOWNTO 0); SIGNAL COUNTER:INTEGER RANGE 0 TO 140; SIGNAL COUNTER1:INTEGER RANGE 0 TO 3;
SIGNAL COUNTER2:INTEGER RANGE 1 TO 10000000; SIGNAL DIGIT :STD_LOGIC_VECTOR(6 DOWNTO 0); SIGNAL COUNT :STD_LOGIC_VECTOR(1 DOWNTO 0); SIGNAL CARRIER,CLK_4MHZ,CLK_4HZ:STD_LOGIC; BEGIN PROCESS(CLK) BEGIN
IF CLK'EVENT AND CLK='1' THEN
IF COUNTER1=1 THEN CLK_4MHZ<='1'; COUNTER1<=2;
ELSIF COUNTER1=3 THEN CLK_4MHZ<='0'; COUNTER1<=0;
ELSE COUNTER1<=COUNTER1+1; END IF;
IF COUNTER2=5000000 THEN CLK_4HZ<='1';
COUNTER2<=5000001;
ELSIF COUNTER2=10000000 THEN CLK_4HZ<='0'; COUNTER2<=1;
ELSE COUNTER2<=COUNTER2+1; END IF; END IF; END PROCESS;
PROCESS(CLK_4MHZ) BEGIN
IF CLK_4MHZ'EVENT AND CLK_4MHZ='1' THEN IF DRIVER=\ CARRIER<='1'; DRIVER<=ORIGIN; ELSE
DRIVER<=DRIVER+1; CARRIER<='0'; END IF; END IF; END PROCESS;
PROCESS(CARRIER)
BEGIN if(p='1')then
IF CARRIER'EVENT AND CARRIER='1' THEN COUNT<=COUNT+1; IF COUNT=\SPEAKER<='1'; ELSE
SPEAKER<='0'; END IF; END IF; end if;
END PROCESS;
PROCESS(CLK_4HZ) BEGIN
IF CLK_4HZ'EVENT AND CLK_4HZ='1' THEN IF COUNTER=140 THEN COUNTER<=0;
ELSE COUNTER<=COUNTER+1; END IF; END IF;
CASE COUNTER IS