side, AGC gain is mostly smaller than unit gain, so mic_volume need more gain in this case.(-12dB, +12dB): this is symmetrical(-6dB, +18dB): this is up side
3. Select reference level for Lout-AGC.
To make sure the runtime gain varies in our control range, we need reference level.
In this sample, we can select talk at 3m at reference level which corresponding AGC gain
is unit gain. Procedure:
? Play normal voice or talk at 3m. ? Observe DM(0x2366) value.
? Adjust the DM(0x2364) parameter to make sure DM(0x2366) varies about 0x800.
In this case, the value of 0x2364 is as our reference level.
To speed up Lout-AGC convergence time, can adjust parameters in 0x2362 and 0x2363 For Lout-DRC module,
1. Select expected output level by parameter 0x23D3. Output level range is 0x~ 0X7FFF.
If you expected output range is PSL (about 0x2000), you can set 0x23D3 = PSL/4 (about 0x800) Certainly you can set some smaller to get more remarkable result. 2. Select control speed of DRC by parameter 0x23D4. The bigger value means faster convergence.
Sep 20, 2012 36 UCM-FM1288 V06
8.0 FM-1288 Parameter Table
Table 14: FM-1288 Parameter Table
Control Address Name Description Value
0x22C0 _i2s0_L_tx_p Reserved 0x0004 0x22C1 _i2s0_R_tx_p Reserved 0x0004 0x22C2 _i2s1_L_tx_p Reserved 0x0003 0x22C3 _i2s1_R_tx_p Reserved 0x0003
LDO 0x22C4 _LDO_ctl_stat Refer to definition of HW MMR
register:0x3FD2 0x0620
CODEC 0x22C5 _mic_addgain_ctl Refer to definition of HW MMR
register:0x3FC0: bit[14,13,8] bit[14:13], select additional gain (10) bit[8], select if apply additional gain (1: means \apply\0x4100
Clock 0x22C6 _CODEC_CLK_div DIV_1: clock divider for CODEC. Range in
0x5 ~ 0x7F 0x000C
Clock 0x22C7 _CODEC_CLK_mul MUL_0: clock multiplier for CODEC. Range
in 0x5 ~ 0xFF or 0 (0 means 256) 0x000C
Clock 0x22C8 _PLL_div_type MCLK(main clock dource) description:
Bit[5]: 1 means MCLK is multiplier of 2.048MHz,0 means else; Bit[4~0]: DIV_0: PLL input divider. Select DIV_0, DIV_1(para 0x22C6), MUL_0(para 0x22C7) to gurantee: MCLK * MUL_0 /(DIV_1 * DIV_0) = 2.048M if Bit[5]=1,then only need to gurantee MCLK/DIV_0=2.048M 0x002C
0x22C9 _PLL_xtal_clk Whether PLL is bypassed:0: DSP clock is from PLL,1: PLL bypassed(DSP clock equals to input MCLK) 0x0000
Clock 0x22CA _chi_CLK_set Refer to definition of HW MMR
register:0x3FF0 bit[15:8]:FCLK,
bit[7:0]:BCLK BCLK setting for PCM in 16K system. FORMULA: BCLK = 4.096Mhz/2*(chi_BCLK_set+1) FCLK setting for PCM in 16K system. FORMULA:
FCLK = BCLK/(chi_FCLK_set+1)
#FORMULA: FCLK=BCLK/(chi_FCLK_set+1) 0x1F03
0x22CB _reserved11 0x0000
0x22CC _chi_CLK_set_8k Refer to definition of HW MMR register:0x3FF0 bit[15:8]:FCLK,
bit[7:0]:BCLK BCLK setting for PCM in 8K system. FORMULA:BCLK =
4.096Mhz/2*(chi_BCLK_set_8K+1) FCLK setting for PCM in 8K system. FORMULA: FCLK = BCLK/(chi_FCLK_set_8K+1) #FORMULA: 0x1F07
Sep 20, 2012 37 UCM-FM1288 V06
Control Address Name Description Value
FCLK=BCLK/(chi_FCLK_set_8K+1) 0x22CD _reserved12 0x0000
0x22CE _i2s_CLK_set Refer to definition of HW MMR register:0x3FF1 bit[15:8]:LRLK,
bit[7:0]:BCLK BCLK setting for I2S in16K system. FORMULA: BCLK = 4.096Mhz/2*(i2s_BCLK_set+1) LRCK setting for I2S in 16K system.
FORMULA:LRCK = BCLK/2*(_i2s_LRCK_set + 1) #FORMULA:
LRCK=BCLK/2*(_i2s_LRCK_set+1) 0x0F03
0x22CF _reserved13 0x0000
0x22D0 _i2s_CLK_set_8k Refer to definition of HW MMR register:0x3FF1 bit[15:8]:LRLK, bit[7:0]:BCLK BCLK setting for I2S in 8K system. FORMULA:BCLK =
4.096Mhz/2*(_i2s_BCLK_set_8k+1) LRCK setting for I2S in 8K system. FORMULA:LRCK =
BCLK/2*(i2s_LRCK_set_8K + 1) #FORMULA:
LRCK=BCLK/2*(i2s_LRCK_set_8K+1) 0x0F07
0x22D1 _reserved14 0x0000
0x22D2 _i2s_special_Mode Reserved 0x0294
0x22D3 _AVC_SNR_thrd Works when Bit[4] of 0x2305 is ON SNR
threshold to trigger BVE, smaller value means harder to trigger BVE 0x0003
0x22D4 _AVC_vol_thrd Works when Bit[4] of 0x2305 is ON The threshold to trigger frequency
adjustment(decrease low and increase high freuqency). When avc_gain_out >threshold, it will trigger the frequency adjustment. DM address for avc_gain_out: 0x380F 0x2000
0x22D5 _SCL_Speed Control speed of eeprom read operation, default: 0x20 Need change before eeprom read(power-on, time relies on MCLK) 0x0040
0x22D6 _read_eeprom_times Control fail-retry times of eeprom read operation, (times= 3 - dm(0x22D6)), range:0~3 Need change before eeprom read(power-on, time relies on MCLK) 0x0004
0x22D7 _reserve_22D7[0] 0x0000 0x22D8 _reserve_22D7[1] 0x0000 0x22D9 _reserve_22D7[2] 0x0000 0x22DA _reserve_22D7[3] 0x0000 0x22DB _reserve_22D7[4] 0x0000 0x22DC _reserve_22D7[5] 0x0000 0x22DD _reserve_22D7[6] 0x0000 0x22DE _reserve_22D7[7] 0x0000 Sep 20, 2012 38 UCM-FM1288 V06
Control Address Name Description Value
0x22DF _reserve_22D7[8] 0x0000
0x22E0 _gain_state_thrd Works when Bit[1] of sp_flag is ON Controls how easy a peak is identified as an \peak\0x3200
0x22E1 _gain_adjust1_dB Works when Bit[1] of sp_flag is ON If an \attenuated by this amount if vad01 is ON 0x4400
0x22E2 _gain_adjust2_dB Works when Bit[1] of sp_flag is ON If an \attenuated by this amount if vad01 is OFF 0x3000
Volume
0x22E3 _vol_inc_step Volume step size. Default is 0dB, it means if 0x22e3 is increased by 0x1, the spk volume will be decreased by 0dB. 0x7FFF
0x22E4 _vol_index This parameter will be set by the host. The number must be 1-9, 1 means max volume, 9 means min volume. Response time <=8ms.
#RANGE: 0x1-0x9 0x0001
ADC
0x22E5 _adc_pga_gain Refer to definition of HW MMR register:0x3FC2 bit[11:8], lin, bit[7:4], mic1, bit[3:0], mic0 0x0222
0x22E6 _adc_vol_mute Refer to definition of HW MMR register:0x3FC3 bit[8] control ADC clock bit[7:1] control mute bit[0] control DAC clock 0x0000
DAC
0x22E7 _dac_vol_ctl Refer to definition of HW MMR register:0x3FC4 bit[15:8] control SPK vol bit[7:0] control LOUT vol 0x0000
0x22E8 _dac_vol_mute Refer to definition of HW MMR register:0x3FC5 bit[7:1] control DAC mute 0x0000
0x22E9 _dac_pga_gain Refer to definition of HW MMR register:0x3FC6 bit[7:4], lout, bit[3:0], spk 0x0011
GPIO 0x22EA _gpio_ctl_set Refer to definition of HW MMR
register:0x3FE6 0x000C
0x22EB _Bypass123_rate_config Reserved 0x07D0
Volume
0x22EC _vol_inc_step_gpio the volume step for GPIO control vol up/down 0x0040
0x22ED _spk_volume_cap_gpio the volume cap for GPIO control vol