16位超前进位加法器的verilog代码：
module fulladder16(sum,c_out,a,b,c_in); output [15:0] sum; output c_out; input [15:0] a,b; input c_in; wire c3,c7,c11,c15;
fulladder4 i1(sum[3:0],c3,a[3:0],b[3:0],c_in); fulladder4 i2(sum[7:4],c7,a[7:4],b[7:4],c3); fulladder4 i3(sum[11:8],c11,a[11:8],b[11:8],c7); fulladder4 i4(sum[15:12],c15,a[15:12],b[15:12],c11); assign c_out=c15; endmodule
module fulladder4(sum,c_out,a,b,c_in); output [3:0] sum; output c_out; input [3:0] a,b; input c_in;
wire p0,g0,p1,g1,p2,g2,p3,g3; wire c1,c2,c3,c4; assign p0=a[0]^b[0], p1=a[1]^b[1],
p2=a[2]^b[2], p3=a[3]^b[3];
assign g0=a[0]&b[0], g1=a[1]&b[1], g2=a[2]&b[2], g3=a[3]&b[3];
assign c1=g0|(p0&c_in),
c2=g1|(p1&g0)|(p1&p0&g0)|(p2&p1&p0&c_in), c3=g2|(p2&g1)|(p2&p1&g0)|(p3&p2&p1&p0&c_in),
c4=g3|(p3&g2)|(p3&p2&g1)|(p3&p2&p1&g0)|(p3&p2&p1&p0&c_in);
assign sum[0]=p0^c_in, sum[1]=p1^c1, sum[2]=p2^c2, sum[3]=p3^c3;
assign c_out=c4; endmodule
附录2 激励块代码如下：
module top; reg[15:0] a,b; reg c_in; wire[15:0] sum; wire c_out;
fulladder16 adder(.sum(sum),.c_out(c_out),.a(a),.b(b),.c_in(c_in)); initial begin
a=5;b=4;c_in=0; #5 a=2;b=6;c_in=1;
#5 a=4'b1101;b=4'b0011;c_in=0;
#5 a=8'b1101_0011;b=8'b0110_0001;c_in=1;
#5 a=12'b0101_1100_0101;b=12'b1100_0000_0101;c_in=0;
#5 a=16'b1011_0001_1100_1010;b=16'b1100_0000_0011_0000;c_in=1; end endmodule