isync
lwz r6, IMMRBAR(r3) //r6= 0xe000000
isync
3.1.4 初始化e300
init_e300_core: /* time t 10 */ /* Initialize machine status; enable machine check interrupt */ li
r3, MSR_KERNEL
/* Set ME and RI flags */
rlwimi r3, r5, 0, 25, 25
/* preserve IP bit set by HRCW,设置中断偏移量 */
#ifdef DEBUG
rlwimi
r3, r5, 0, 21, 22 /* debugger might set SE & BE bits */
#endif SYNC
/* Some chip revs need this... */ mtmsr r3
/*保存到MSR*/
SYNC mtspr
SRR1, r3
/* Make SRR1 match MSR */
//禁止看门狗
lis r3, CONFIG_SYS_IMMR@h
#if defined(CONFIG_WATCHDOG) //如果看门狗宏定义了则启用它
/* Initialise the Wathcdog values and reset it (if req) */ /*------------------------------------------------------*/ lis r4, CONFIG_SYS_WATCHDOG_VALUE
ori r4, r4, (SWCRR_SWEN | SWCRR_SWRI | SWCRR_SWPR)
26
stw r4, SWCRR(r3)
/* and reset it */
li r4, 0x556C
sth r4, SWSRR@l(r3) li
r4, -0x55C7
sth r4, SWSRR@l(r3)
#else
//禁止看门狗 /* Disable Wathcdog */ /*-------------------*/ lwz r4, SWCRR(r3)
/* Check to see if its enabled for disabling once disabled by SW you can't re-enable */ andi. r4, r4, 0x4 beq 1f xor r4, r4, r4 stw r4, SWCRR(r3)
1:
#endif /* CONFIG_WATCHDOG */
########设置HID###################
27
lis r3, CONFIG_SYS_HID0_INIT@h ori r3, r3, (CONFIG_SYS_HID0_INIT | HID0_ICFI | HID0_DCFI)@l SYNC mtspr
HID0, r3
lis r3, CONFIG_SYS_HID0_FINAL@h
ori r3, r3, (CONFIG_SYS_HID0_FINAL & ~(HID0_ICFI | HID0_DCFI))@l SYNC mtspr
HID0, r3
lis r3, CONFIG_SYS_HID2@h ori r3, r3, CONFIG_SYS_HID2@l SYNC mtspr
HID2, r3
/* Done! */
/*------------------------------*/ Blr
//
返回
3.1.5 窗口设置 map_flash_by_law1: /* When booting from ROM (Flash or EPROM), clear the */ /* Address Mask in OR0 so ROM appears everywhere */
/*----------------------------------------------------*/
28
lis r3, (CONFIG_SYS_IMMR)@h /* r3= 0xe0000000 */ lwz r4, OR0@l(r3) li
r5, 0x7fff /* r5= 0x0007FFF */
and r4, r4, r5
stw r4, OR0@l(r3) /* OR0 = OR0 & 0x0000_7FFF */
/* As MPC8349E User's Manual presented, when RCW[BMS] is set to 0, * system will boot from 0x0000_0100, and the LBLAWBAR0[BASE_ADDR] * reset value is 0x00000; when RCW[BMS] is set to 1, system will boot * from 0xFFF0_0100, and the LBLAWBAR0[BASE_ADDR] reset value is * 0xFF800. From the hard resetting to here, the processor fetched and * executed the instructions one by one. There is not absolutely * jumping happened. Laterly, the u-boot code has to do an absolutely * jumping to tell the CPU instruction fetching component what the * u-boot TEXT base address is. Because the TEXT base resides in the * boot ROM memory space, to garantee the code can run smoothly after * that jumping, we must map in the entire boot ROM by Local Access * Window. Sometimes, we desire an non-0x00000 or non-0xFF800 starting * address for boot ROM, such as 0xFE000000. In this case, the default * LBIU Local Access Widow 0 will not cover this memory space. So, we * need another window to map in it. */
lis r4, (CONFIG_SYS_FLASH_BASE)@h ori r4, r4, (CONFIG_SYS_FLASH_BASE)@l
29
stw r4, LBLAWBAR1(r3) /* LBLAWBAR1 = CONFIG_SYS_FLASH_BASE */
/* Store 0x80000012 + log2(CONFIG_SYS_FLASH_SIZE) into LBLAWAR1 */ lis r4, (0x80000012)@h ori r4, r4, (0x80000012)@l li r5, CONFIG_SYS_FLASH_SIZE
1: srawi. r5, r5, 1 /* r5 = r5 >> 1 */
remap_flash_by_law0:
/* Initialize the BR0 with the boot ROM starting address. */ lwz r4, BR0(r3) li r5, 0x7FFF and r4, r4, r5
lis r5, (CONFIG_SYS_FLASH_BASE & 0xFFFF8000)@h ori r5, r5, (CONFIG_SYS_FLASH_BASE & 0xFFFF8000)@l or r5, r5, r4
stw r4, LBLAWAR1(r3) /* LBLAWAR1 <= 8MB Flash Size */ blr
addi r4, r4, 1 bne 1b
stw r5, BR0(r3) /* r5 <= (CONFIG_SYS_FLASH_BASE & 0xFFFF8000) | (BR0 & 0x00007FFF) */
30