EPwm2Regs.TBCTL.bit.CTRMODE = TB_COUNT_UPDOWN; EPwm2Regs.TBCTL.bit.PHSEN = TB_DISABLE;
EPwm2Regs.TBCTL.bit.HSPCLKDIV = TB_DIV1; EPwm2Regs.TBCTL.bit.CLKDIV = TB_DIV1;
EPwm2Regs.CMPCTL.bit.SHDWAMODE = CC_SHADOW; EPwm2Regs.CMPCTL.bit.SHDWBMODE = CC_SHADOW;
EPwm2Regs.CMPCTL.bit.LOADAMODE = CC_CTR_ZERO_PRD; EPwm2Regs.CMPCTL.bit.LOADBMODE = CC_CTR_ZERO_PRD;
EPwm2Regs.AQCTLA.bit.CAU = AQ_CLEAR; EPwm2Regs.AQCTLA.bit.CAD = AQ_SET; EPwm2Regs.AQCTLB.bit.CAU = AQ_SET; EPwm2Regs.AQCTLB.bit.CAD = AQ_CLEAR;
EPwm2Regs.ETSEL.bit.INTSEL = ET_CTR_ZERO; EPwm2Regs.ETSEL.bit.INTEN = 1;
EPwm2Regs.ETPS.bit.INTPRD = ET_1ST; EPwm1Regs.DBCTL.all = 0xb; EPwm1Regs.DBRED = 60; EPwm1Regs.DBFED = 60; }
interrupt void epwm1_timer_isr(void) {
if(k >= 400) { k = 0; }
EPwm1Regs.CMPA.half.CMPA = TonC[k]; EPwm1Regs.CMPB = TonC[k]; k++;
EPwm1Regs.ETCLR.bit.INT = 1;
PieCtrlRegs.PIEACK.all = PIEACK_GROUP3; }
interrupt void epwm2_timer_isr(void) {
if(k >= 400) { k = 0; }
EPwm2Regs.CMPA.half.CMPA = TonC[k]; EPwm2Regs.CMPB = TonC[k]; k++;
EPwm2Regs.ETCLR.bit.INT = 1;
PieCtrlRegs.PIEACK.all = PIEACK_GROUP3; }