MIPS单周期CPU实验报告 - 图文(3)

计算机组成原理实验

45. RD = 1; 46. WR = 1; 47. RegDst = 0; 48. ExtSel = 1; 49. ALUOp = 3'b000; 50. end

51. 6'b000010:begin //sub 52. PCWre = 1; 53. ALUSrcA = 0; 54. ALUSrcB = 0; 55. DBDataSrc = 0; 56. RegWre = 1; 57. InsMemRW = 1; 58. RD = 1; 59. WR = 1; 60. RegDst = 1; 61. ALUOp = 3'b001; 62. end

63. 6'b010000:begin // ori 64. PCWre = 1; 65. ALUSrcA = 0; 66. ALUSrcB = 1; 67. DBDataSrc = 0; 68. RegWre = 1; 69. InsMemRW = 1; 70. RD = 1; 71. WR = 1; 72. RegDst = 0; 73. ExtSel = 0; 74. ALUOp = 3'b011; 75. end

76. 6'b010001:begin //and 77. PCWre = 1; 78. ALUSrcA = 0; 79. ALUSrcB = 0; 80. DBDataSrc = 0; 81. RegWre = 1; 82. InsMemRW = 1; 83. RD = 1; 84. WR = 1; 85. RegDst = 1; 86. ALUOp = 3'b100; 87. end

88. 6'b010010:begin // or

计算机组成原理实验

89. PCWre = 1; 90. ALUSrcA = 0; 91. ALUSrcB = 0; 92. DBDataSrc = 0; 93. RegWre = 1; 94. InsMemRW = 1; 95. RD = 1; 96. WR = 1; 97. RegDst = 1; 98. ALUOp = 3'b011; 99. end

100. 6'b011000:begin //sll 101. PCWre = 1; 102. ALUSrcA = 1; 103. ALUSrcB = 0; 104. DBDataSrc = 0; 105. RegWre = 1; 106. InsMemRW = 1; 107. RD = 1; 108. WR = 1; 109. RegDst = 1; 110. ALUOp = 3'b010; 111. end

112. 6'b011100:begin //slt 113. PCWre = 1; 114. ALUSrcA = 0; 115. ALUSrcB = 0; 116. DBDataSrc = 0; 117. RegWre = 1; 118. InsMemRW = 1; 119. RD = 1; 120. WR = 1; 121. RegDst = 1; 122. ALUOp = 3'b110; 123. end

124. 6'b100110:begin //sw 125. PCWre = 1; 126. ALUSrcA = 0; 127. ALUSrcB = 1; 128. RegWre = 0; 129. InsMemRW = 1; 130. RD = 1; 131. WR = 0; 132. ExtSel =1;

计算机组成原理实验

133. ALUOp = 3'b000; 134. end

135. 6'b100111:begin //lw 136. PCWre = 1; 137. ALUSrcA = 0; 138. ALUSrcB = 1; 139. DBDataSrc = 1; 140. RegWre = 1; 141. InsMemRW = 1; 142. RD = 0; 143. WR = 1; 144. RegDst = 0; 145. ExtSel = 1; 146. ALUOp = 3'b000; 147. end

148. 6'b110000:begin //beq 149. PCWre = 1; 150. ALUSrcA = 0; 151. ALUSrcB = 0; 152. RegWre = 0; 153. InsMemRW = 1; 154. RD = 1; 155. WR = 1; 156. ExtSel = 1; 157. ALUOp = 3'b001; 158. end

159. 6'b110001:begin //bne 160. PCWre = 1; 161. ALUSrcA = 0; 162. ALUSrcB = 0; 163. RegWre = 0; 164. InsMemRW = 1; 165. RD = 1; 166. WR = 1; 167. ExtSel = 1; 168. ALUOp = 3'b001; 169. end

170. 6'b110010:begin 171. PCWre = 1; 172. ALUSrcA = 0; 173. ALUSrcB = 0; 174. RegWre = 0; 175. InsMemRW = 1; 176. RD = 1;

计算机组成原理实验

177. WR = 1; 178. ExtSel = 1; 179. ALUOp = 3'b001; 180. end

181. 6'b111000:begin //j 182. PCWre = 1; 183. RegWre = 0; 184. InsMemRW = 1; 185. RD = 1; 186. WR = 1;

187. ALUOp = 3'b010; 188. end

189. 6'b111111:begin //halt 190. PCWre = 1; 191. RegWre = 0; 192. InsMemRW = 1; 193. RD = 1; 194. WR = 1; 195. end

196. default:begin 197. RD = 1; 198. WR = 1; 199. RegWre = 0; 200. InsMemRW = 0; 201. end 202. endcase 203. end

204. always@(opcode or zero or sign) begin 205. if(opcode == 6'b111000) // j 206. PCSrc = 2'b10;

207. else if(opcode[5:3] == 3'b110) begin 208. if(opcode[2:0] == 3'b000) begin 209. if(zero == 1) 210. PCSrc = 2'b01; 211. else

212. PCSrc = 2'b00; 213. end

214. else if(opcode[2:0] == 3'b001) begin 215. if(zero == 0) 216. PCSrc = 2'b01; 217. else

218. PCSrc = 2'b00; 219. end 220. else begin

计算机组成原理实验

221. if(zero == 0 && sign == 0) 222. PCSrc = 2'b01; 223. else

224. PCSrc = 2'b00; 225. end 226. end 227. else begin

228. PCSrc = 2'b00; 229. end 230. end 231. endmodule

仿真截图：

（2）程序计数器（PC） Verilog代码：

1. module PC( 2. input clk,

3. input [31:0] PCin, 4. input PCWre, 5. input Reset,

6. output reg [31:0] PCout 7. );

8. initial begin 9. PCout <= 0; 10. end

11. always@(posedge clk) begin 12. if(Reset == 0) begin 13. PCout <= 0; 14. end

15. else if(PCWre == 0) begin 16. PCout <= PCout; 17. end 18. else begin