致谢
在大学学习生活即将结束之际，对四年来曾关心、指导、帮助和鼓励过我的老师、同学们表示衷心的感谢。让我们共同分享完成论文的喜悦。
感谢指导老师金震妮老师在论文的选题、实验设计与论文的撰写过程中，自始至终以严谨的治学作风和崇高的责任心给予了全面的指导。金震妮老师对科研工作的执著和奉献精神将是我终生学习的楷模。同时也感谢班级同学及其他老师在设备和实验方面给予的帮助。感谢我的朋友们在我四年本科生的学习、工作和生活中对我的支持、理解与鼓励。最后，祝愿所有老师和同学在今后的工作、学习和生活中事事顺心，心想事成。
作者：
2012年6月13日
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参考文献
[1]刘志强，罗庆生．一种智能化温度检测系统的设计[J]．中国测试技术，2003，29(3)：95-98
[2]阳成军．用单总线器件组建温湿度测控系统硬件设计[J]．传感器世界2004(2) ：38-39
[3] 李建民.单片机在温度控制系统中的应用[J].江汉大学学报,1996.06 [4] 孙良言.国外湿度传感器发展动态[J].传感器世界, 1997.12
[5] 孙宁.基于GSM模块的远程温湿度监控系统[J].世界科技研究与发展,2002 [6] 倪自强.Lab view环境下温湿度监控系统实现[J].电子元器件应用2009.02 [7] 刘春起.居室温湿度监控系统设计[J].石家庄职业技术学院报,2007
[8] 刘艳玲．采用MAX232实现MCS-51单片机与PC机的通信[J]．天津理工学院学报，1999
[9]. 薛玲，孙曼，张志会，夏莉丽，魏希文.基于单片机AT89S51的温湿度控制仪 [J].2010, 37, (7):66-69.
[10] 刘宝元，张玉虹，姜旭，段存丽.基于单片机的温湿度监控系统设计[J].国外电子测量技术，2009，（12）：77-80,83.
[11] 张友德 . 单片微型机原理、应用与实验[M].复旦大学出版社.2001 [12] 曹琳琳 .单片机原理及接口技术[M].国防科技大学出版社.2003
[13] Gerand N.Stenbakken.Awideband Sampling WatmeterI EEE Tras on Power Ap –paratus And System[ M]1984,PA S-103(10):2919--2925
[14] T.S.Rathoke.Theorems on Power M an and RMS Values of Uniformly Sampled Peirodic Signals IEE Proc.SCIENCE[ J]1984 131(3):598-600
[15] Zhao Yongzhong etc. ZWB-2 intelligent millimeters[M], Intelligent Processing Systems[M] 1997.
[16] Microelectronics Analog Communications Handbook[M]. MITEL,1991 [17] ISD公司，ISD data sheet [J] www.21IC.com
[18] Roland E.Best Electronic Measurement Technology by McGraw-hill Education(Asia) Co[M]. 1997
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LCD1LM016LVSSVDDVEERSRWE7891011121314D0D1D2D3D4D5D6D7P1.74P1.656C1123RP111nF19XTAL1CRYSTAL18XTAL21nFX1U1C2S17C330PFRST9P0.0/AD0P0.1/AD1P0.2/AD2P0.3/AD3P0.4/AD4P0.5/AD5P0.6/AD6P0.7/AD7RESPACK-8393837363534333223456789R3U232SCKDATA>R110kP2.7293031PSENALEEA10k80.027.0%RHP2.0/A8P2.1/A9P2.2/A10P2.3/A11P2.4/A12P2.5/A13P2.6/A14P2.7/A15SHT112122232425262728癈
附录A温湿度监控系统仿真图
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S2S6AT89C51S4S5S9S13LS1SPEAKERS3S1123456P1.67P1.78P1.0/T2P1.1/T2EXP1.2P1.3P1.4P1.5P1.6P1.7P3.0/RXDP3.1/TXDP3.2/INT0P3.3/INT1P3.4/T0P3.5/T1P3.6/WRP3.7/RD10111213141516171C1+C41nF3C1-T1OUTR1IN1112109T1INR1OUTT2INR2OUTT1OUTR1INT2OUTR2INVS+VS-C2+C2-141378261uFS8S10S14S7U3S12S11S16S15C6P2.71kR2Q1PNPC745MAX232C51nF1uF
附录B外文文献及译文
Brief Introduction of AT89C51
The AT89C51 is a low-power, high-performance CMOS 8-bit microcomputer with 4K bytes of Flash Programmable and Erasable Read Only Memory (PEROM) and 128 bytes RAM. The device is manufactured using Atmel’s high density nonvolatile memory technology and is compatible with the industry standard MCS-51? instruction set and pin out. The chip combines a versatile 8-bit CPU with Flash on a monolithic chip; the Atmel AT89C51 is a powerful microcomputer which provides a highly flexible and cost effective solution to many embedded control applications.
Features:
Compatible with MCS-51? Products
4K Bytes of In-System Reprogrammable Flash Memory Endurance: 1,000 Write/Erase Cycles Fully Static Operation: 0 Hz to 24 MHz Three-Level Program Memory Lock 128 x 8-Bit Internal RAM 32 Programmable I/O Lines Two 16-Bit Timer/Counters Six Interrupt Sources
Programmable Serial Channel
Low Power Idle and Power Down Modes
The AT89C51 provides the following standard features: 4K bytes of Flash, 128 bytes of RAM, 32 I/O lines, two 16-bit timer/counters, a five vector two-level interrupt architecture, a full duplex serial port, on-chip oscillator and clock circuitry. In addition, the AT89C51 is designed with static logic for operation down to zero frequency and supports two software selectable power saving modes. The Idle Mode stops the CPU while allowing the RAM, timer/counters, serial port and interrupt system to continue functioning. The Power down Mode saves the RAM contents but freezes the oscillator disabling all other chip functions until the next hardware reset.
Pin Description:
VCC Supply voltage. GND Ground. Port 0
Port 0 is an 8-bit open drain bidirectional I/O port. As an output port each pin can sink eight TTL inputs. When is written to port 0 pins, the pins can be used as high impedance inputs.
Port 0 may also be configured to be the multiplexed low order address/data bus
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during accesses to external program and data memory. In this mode P0 has internal pull-ups.
Port 0 also receives the code bytes during Flash programming, and outputs the code bytes during program verification. External pull-ups are required during program verification.
Port 1
Port 1 is an 8-bit bidirectional I/O port with internal pull-ups. The Port 1 output buffers can sink/source four TTL inputs. When 1s are written to Port 1 pins they are pulled high by the internal pull-ups and can be used as inputs. As inputs, Port 1 pins that are externally being pulled low will source current (IIL) because of the internal pull-ups. Port 1 also receives the low-order address bytes during Flash programming and verification.
Port 2
Port 2 is an 8-bit bidirectional I/O port with internal pull-ups. The Port 2 output buffers can sink/source four TTL inputs. When 1s are written to Port 2 pins they are pulled high by the internal pull-ups and can be used as inputs. As inputs, Port 2 pins that are externally being pulled low will source current (IIL) because of the internal pull-ups. Port 2 emits the high-order address byte during fetches from external program memory and during accesses to external data memory that uses 16-bit addresses (MOVX @ DPTR). In this application it uses strong internal pull-ups when emitting 1s. During accesses to external data memory that uses 8-bit addresses (MOVX @ RI), Port 2 emits the contents of the P2 Special Function Register.
Port 2 also receives the high-order address bits and some control signals during Flash programming and verification.
Port 3
Port 3 is an 8-bit bidirectional I/O port with internal pull-ups. The Port 3 output buffers can sink/source four TTL inputs. When 1s are written to Port 3 pins they are pulled high by the internal pull-ups and can be used as inputs. As inputs, Port 3 pins that are externally being pulled low will source current (IIL) because of the pull-ups. Port 3 also serves the functions of various special features of the AT89C51 as listed below: Port 3 also receives some control signals for Flash programming and verification.
RST
Reset input. A high on this pin for two machine cycles while the oscillator is running resets the device.
ALE/PROG
Address Latch Enable output pulse for latching the low byte of the address during accesses to external memory. This pin is also the program pulse input (PROG)
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