library ieee;
use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all;
entity f_sub4_2 is
GENERIC (n : INTEGER := 4); port(
a,b : IN STD_LOGIC_VECTOR(n-1 DOWNTO 0); cin : IN std_logic;
diff: out STD_LOGIC_VECTOR(n-1 DOWNTO 0); Cout: OUT std_logic ); end;
architecture a of f_sub4_2 is component f_sub1 is port(
a,b,cin : IN std_logic; diff,Cout : OUT std_logic ); end component;
signal c :STD_LOGIC_VECTOR(n DOWNTO 0); begin c(0)<=cin;
n1: for i in 0 to n-1 generate
U1: f_sub1 port map(a(i),b(i),c(i),diff(i),c(i+1)); end generate; cout<=c(n); end a;
5-17用VHDL语言设计实现输出占空比为50%的1000分频器。
library ieee;
use ieee.std_logic_1164.all; entity div_1000 is port(
clk ,clr: in std_logic; div : out std_logic ); end;
architecture a of div_1000 is signal q : std_logic; begin div<=q;
process(clk,clr)
variable cnt : integer range 0 to 499; begin
if clr='1' then cnt:=0; q<='0';
elsif rising_edge(clk) then if cnt=499 then cnt:=0; q<=not q; else
cnt:=cnt+1; end if; end if; end process;