end if; end case; end if;
end process transmit; --specified by datasheet
power_on_initialize: process(clk, rst_n, init_init) --power on initialization sequence begin if(rst_n='0') then init_state <= idle; init_done <= '0'; elsif(clk='1' and clk'event) then case init_state is when idle => init_done <= '0'; if(init_init = '1') then init_state <= fifteenms; i <= 0; else init_state <= idle; i <= i + 1; end if; when fifteenms => init_done <= '0'; if(i = 750000) then init_state <= one; i <= 0; else init_state <= fifteenms; i <= i + 1; end if; when one => SF_D1 <= \ LCD_E1 <= '1'; init_done <= '0'; if(i = 11) then init_state<=two; i <= 0; else init_state<=one; i <= i + 1; end if; when two => LCD_E1 <= '0'; init_done <= '0';
if(i = 205000) then init_state<=three; i <= 0; else init_state<=two; i <= i + 1; end if; when three => SF_D1 <= \ LCD_E1 <= '1'; init_done <= '0'; if(i = 11) then init_state<=four; i <= 0; else init_state<=three; i <= i + 1; end if; when four => LCD_E1 <= '0'; init_done <= '0'; if(i = 5000) then init_state<=five; i <= 0; else init_state<=four; i <= i + 1; end if; when five => SF_D1 <= \ LCD_E1 <= '1'; init_done <= '0'; if(i = 11) then init_state<=six; i <= 0; else init_state<=five; i <= i + 1; end if; when six => LCD_E1 <= '0'; init_done <= '0'; if(i = 2000) then init_state<=seven;
i <= 0; else init_state<=six; i <= i + 1; end if; when seven => SF_D1 <= \ LCD_E1 <= '1'; init_done <= '0'; if(i = 11) then init_state<=eight; i <= 0; else init_state<=seven; i <= i + 1; end if; when eight => LCD_E1 <= '0'; init_done <= '0'; if(i = 2000) then init_state<=done; i <= 0; else init_state<=eight; i <= i + 1; end if; when done => init_state <= done; init_done <= '1'; end case; end if; end process power_on_initialize; end behavior;
因为LCD模块无法仿真，故在此不做仿真
四、实验总结
1、心得体会
此次设计实验是对本课程的一次总结，通过此次实验大大提高了自己的动手能力，对VHDL这门语言以及对FPGA的开发油了更加深入的了解
在动手设计实验的过程中，也遇到了很多问题，比如计数器工作不正常，LED
灯非正常闪烁，也用了了很大的功夫才把BUG解决。
课程设计给了我们把知识转化为能力的机会，这次电子技术课程设计更是让我受益良多。
其次本次试验也存在很多不足之处，如按键抖动的问题，还有红灯的计算模块都有欠缺考虑之处。还需要改进。