VHDL编写testbench（.vht文件）
对modelsim自己产生的.vht文件修改进行仿真时，需要更改两处，分别是如下：
1. 对于Signal信号需要赋初值。 例如： 原文件中：
SIGNAL CLK_IN : STD_LOGIC;
SIGNAL Q : STD_LOGIC_VECTOR(3 DOWNTO 0); 更改后为：
SIGNAL CLK_IN : STD_LOGIC := '1';
SIGNAL Q : STD_LOGIC_VECTOR(3 DOWNTO 0) := \
2. 激励信号赋值方式。 对于初始只进行一次的赋值 对于需要周期性的赋值 process_init : PROCESS process_always : PROCESS BEGIN BEGIN RST_N <= '1'; WAIT FOR 20NS; CLK_IN <= '0'; WAIT FOR 10NS; RST_N <=’0’; WAIT FOR 20NS; CLK_IN <= '1'; WAIT FOR 10NS; END PROCESS process_ always; WAIT; END PROCESS process_ init; 最简单的记法，格式都是如下： SIG<=’1’; WAIT FOR 10 NS; SIG<=’0’; WAIT FOR 10 NS;
时钟信号：
process_clk : PROCESS
BEGIN
CLK_IN <= '0'; WAIT FOR 10NS; CLK_IN <= '1'; WAIT FOR 10NS; END PROCESS process_clk;
复位信号：
process_rst : PROCESS
BEGIN
RST_N <= '1'; WAIT FOR 20NS; RST_N <=’0’; WAIT FOR 20NS; WAIT;
END PROCESS process_rst;
一般激励信号：
process_sig : PROCESS
BEGIN SIG<=’1’; WAIT FOR 10 NS; SIG<=’0’; WAIT FOR 20 NS;
SIG<=’1’; WAIT FOR 20 NS; SIG<=’0’; WAIT FOR 10 NS; END PROCESS process_ sig;