The W8E58B incorporates a buit-in crystal oscilator. To make the oscillator work , crystal must be connected across pins XTAL1 and XTAL2. In addition, a load capacitor must be connected from each pin to ground.
9. External Clock
A n extenal clock should be connected to pin XTAL1 and XTAL2 should be left unconnected . The XTAL1 input is a COMOS-type input, as requied by the crystal osillator.
10. Power Management
Idle Mode
Setting the IDL bit in the PCON register enters the idle mode. In the mode, the internal clock to the processor is stopped. The peripherals and interrupt logic continue to be clocked. The processor will exit idle mode when wither an interrupt or a reset occurs.
Power-down Mode
When the PD bit in the PCON register is set, the processor enters the power-down mode. In this mode all of the clocks are stopped, including the oscillator. To exit from power-down mode is by a hardware reset or external interrupts INT0 to INT1 when enaled and set to level trigered.
11. Reduce EMI Emission
The W78E58B allows user to diminish the gain of on-chip oscillator amplifer by using programmer to clear the B7 bit of security register. Once B7 is set to 0, a half of gain will be decreased. Care must be taken if user attempts to diminish the gain of oscillator amplifier, reducing a half of gain may affect the external crystsl operating improperly at high frequency. The value of C1 and C2 may need some adjustment while running at lower gain.
12. Rest
The external RESET singlal is sampled at S5P2. To take effect, it must be held high for at least two machine cycles while the oscillator is running. An internal trigger circuit in thereset line is used to deglitch the reset line when the W78E58B is used with an external RC network. The rest logic also has a special glitch removal circuit that ignores glitches on the reset line. During reset, the ports are initialized to FFT, the stack pointer to 07H, PCON(with the exception of bit 4) to 00H, and all of the other SFR register except SBUF to00H. SBUF is not reset.
13. Port 4
Port 4, address D8H, is a4-bit multipore programmable I/O port. Each bit can be configured indiviualy by software. The Port 4 has four different opeation modes.
Mode 0: P4.0—P4.3 is a bit-directional I/O port which is same as port 1. P4.2 and
P4.3 also serve as external interrupt INT3 and INT2 if enabled.
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Mode 1: P4.0—P4.3 are read strobe single signal that are synchronized with RD
signal at specified addresses. These signals can be used as chip-select signals for external peripherals.
Mode 2: P4.0—P4.3 are read strobe single signal that are synchronized with WR
signal at specified addresses. These signals can be used as chip-select signals for external peripherals.
Mode 3: P4.0—P4.3 are read/write storbe signals that are synchronized with RD or
WR singal at specified addresses. The signal can be used as chip-select
signals for external peripherals.
When Port 4is configured with the feature of chip-select signals,the chip-select signal address range depends on the contents of the SFR P4xAL, P4CONA and P4CONB contain the control bits to configure the Port4 operation mode.
14. INT2 and INT3
Two additional external interrupts, INT2 and INT3, whose funtions are similar to those of external interrupt 0 and 1in the standard 80C52. Its address is at 0C0H. To set/clear bits in the XICON register, one can use the ―SETB(CLR) bit‖ instruction. For example, ―SETB 0C2H‖ sets the EX2 bit of XICON. XICON – esternal interrupt control (C0H)
PX3: External interrupt 3 priority high if set EX3: External interrupt 3 enable if set
IE3: If IT3=1, IE3 is set/cleared automatically by hardware when interrupt is
detdcted/serviced
IT3: External interrupt 3 is falling-edge/low-level triggered when this bit is set/cleared
by software
PX2: External interrupt 2 priority high if set EX2: External interrupt 2 enbale if set
IE2: If IT2=1,IE2 is set/cleared automatically by hardware when interrupt is
detected/serviced
IT2: External interrupt 2 is falling-edge/low-level triggered when this bit is
wet/cleared by software
15. Port 4 Base Address Register
P40AH, P40AL
The Base address register for comparator of P4.0. P40AH contains the high-order byte of address, P40AL contains the low-order byte of address.
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P41AH, P41AL
The Base address register for comparator of P4.1. P41AH contains the high-order byte of address, P41AL contains the low-order byte of address. P42AH, P42AL
The Base address register for comparator of P4.2. P42AH contains the high-order byte of address, P42AL contains the low-order byte of address. P43AH, P43AL
The Base address register for comparator of P4.3. P43AH contains the high-order byte of address, P43AL contains the low-order byte of address.
16.In-System Programming(ISP)Mode
The W78E58B equips one 32K byte of main ROM bank for application program(called APROM)and one 4K byte of auxiliary ROM bank for loader program(called LDEOM). In the normal opertaion the microntroller executes the code in the APRON. If the antent of APROM needs to be modified the W78E58B allows user to acctive the In-system programming (ISP)mode by setting the CHPCON resgiter.The CHPCON isread-only by default, software must write two specific values 87H, the 59H sequeutially to the CHPENR register to enable to enable the CHPCON write attribute. Writing CHPENR register with the values except 87H and 59H will close CHPCON register write attribute.The W78E58B achieve all in system programming operations including enter/exit .ISP Mode program,erase..etc. dury device in the idle mode. Setting the bi CHPCON.0 the device will enter in system programming mode after a wake-up from idle mode. Because device needs proper time to complete the ISP operations before awaken from idle mode. Software may use timer interupt ti control the duration for device wake-up from idle mode. To perform ISP operation for revising contents of APROM, software located at APROM setting the CHPCON register then enter idle mode, after awaken from idle mode the device executes the corresponding interrupt service routine in LDROM. Because the debvice will clear the program couter while switching from APROM to LDROM, the first execution of RETI instruction in interrupt service routine will jump to 00H at LDROM area. The device offers a sofware reset for switching back to APROM while the contentof APROM has been update completely. Setting CHPCON register bit 0, 1 and 7to logic-1 will result a software reset to reset the CPU. The software reset serves as a external reset. This in-system programming feature makes the job easy and efficient in which the application needs to update firmware frequently. In some applications, the in-system programming feature make it possible to update to easily update the system firmware without opening the chassis.
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W78E58B芯片规格书
1. 概述
W78E58B是具有带 ISP功能的 Flash EPROM的低功耗8 位微控制器；ISP功能的 Flash EPROM可用于固件升级。它的指令集同标准8052指令集完全兼容。W78E58B包含32K字节的主ROM、4K字节的辅助 ROM。（位于 4K 字节辅助 ROM 中的装载（loader）程序，可以让用户更新位于32K主ROM中的程序内容。）512 字节片内 RAM；4个8位双向、可位寻址的I/O口；一个附加的4位 I/O 口P4；3个16 位定时/计数器及一个串行口。这些外围设备都由有8个中断源和2级中断能力的中断系统支持。为了方便用户进行编程和验证，W78E58B内含的 ROM 允许电编程和电读写。一旦代码确定后，用户就可以对代码进行保护。
W78E58B有2种节电模式，空闲模式和掉电模式，2种模式均可由软件来控制选择。空闲模式下，处理器时钟被关闭，但外设仍继续工作。在掉电模式下晶体振荡器停止工作，以将功耗降至最低。外部时钟可以在任何时间及状态下被关闭，而不影响处理器运行。 2. 特性
? 全静态设计的CMOS 8位微处理器
? 32K字节片内应用程序 ISP Flash EPROM(APROM) ? 4K字节辅助 ROM，装载程序存储器(LDROM)
? 512 字节片内暂存 RAM(包括 256 字节辅助 RAM，软件可选) ? 64KB程序存储器地址空间，64KB数据存储器地址空间 ? 4个8 位双向I/O口 ? 一个 4位可编程 I/O 口 ? 3个16位定时/计数器 ? 一个全双工串行口（UART） ? 8个中断源，2 级中断能力 ? 内建电源管理 ? 降低 EMI模式 ? 代码保护机制 ? 封装:
DIP40: W78E58B-40 PLCC44: W78E58BP-40 PQFP44: W78E58BF-40
无铅封装 DIP40: W78E058B40DL
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无铅封装 PLCC44: W78E058B40PL 无铅封装 PQFP44: W78E058B40FL
3. 管脚描述 符号 EA PSEN ALE RST 描述 外部访问使能：此管脚使处理器访问外部 ROM。当EA保持高电平时， ROM 的地址EA 和数据就不会出现在总线上。 程序存储使能：此管脚允许外ROM数据出现在P0口的地址/数据总线上。当访问内部ROM时，此管脚上不输出PSEN信号。 地址锁存使能：ALE用于将P0口地址锁存，使其和数据分离。 复位：振荡器运行时，此管脚上出现两个机器周期的高电平将使器件复位。 XTAL1 石英晶体1：晶体振荡器的输入。此管脚可由一个外部时钟驱动。 XTAL2 石英晶体2：晶体振荡器的输出。XTAL2 是 XTAL1 的反相端。 VSS VDD P0.0-P0.7 P2.0-P2.7 P3.0-P3.7 地：地电位 电源：电源工作电压 端口1：端口1是一个具有内部上拉电路的双向I/O口。有复用功能位，如下：T2（P1.0）：定时/计数器2的外部计数输入 T2EX（P1.1）定时/计数器2的重装载/捕获控制 端口2：端口2是一个具有内部上拉电路的双向I/O口。此端口提供访问外部存储器的高位地址。 端口3：端口3是一个具有内部上拉电路的双向I/O 口。所有位都有复用功能， 如下： RXD（P3.0）：串行口接收器输入 TXD（P3.1）：串行口发送器输出 0INT （P3.2）：外部中断0 1INT （P3.3）：外部中断1 T0（P3.4）：定时器0外部输入 T1（P3.5）：定时器1外部输入 WR（P3.6）：外部数据存储器写选通 RD（P3.7）：外部数据存储器读选通 P4.0-P4.3 端口4：可位寻址的双向 I/O口P4。P4.3和P4.2为功能复用管脚。它们既可以作为通用的I/O口，也可以作为外部中断源的输入（2INT / 3INT） 45