2. 看下面原理图，写出相应VHDL描述（10分）
xinINPUTDFFORDFFDclkINPUTQDQOUTPUTyout
LIBARRY IEEE;
USE IEEE.STD_LOGIC_1164.ALL; ENTITY MYCIR IS PORT ( XIN, CLK : IN STD_LOGIC; YOUT : OUT STD_LOGIC); END MYCIR;
ARCHITECTURE ONE OF MYCIR IS SIGNAL A, B, C; BEGIN B <= XIN OR A; PROCESS (CLK) BEGIN IF CLK?EVENT AND CLK = ?1? THEN A <= C; C <= B; END IF; END PROCESS; YOUT <= C; END ONE;
第 6 页 共 8 页 六、综合题：（20分） （一） 已知状态机状态图如图(a)所示；完成下列各题： 得分 评阅人
1. 试判断该状态机类型，并说明理由。（2分）
该状态机为moore型状态机，输出数据outa和输入ina没有直接逻辑关系
2. 根据状态图，写出对应于结构图（b），分别由主控组合进程和主控时序进程组成的VHDL有限状态机描述。（10分）
Library ieee;
Use ieee.std_logic_1164.all; Entity mooreb is Port (clk, reset : in std_logic; Ina : in std_logic_vector (1 downto 0); Outa : out std_logic_vector (3 downto 0) ); End mooreb;
Architecture one of mooreb is Type ms_state is (st0, st1, st2, st3); Signal c_st, n_st : ms_state; Begin Process (clk, reset) Begin If reset = ?1? then c_st <= st0; Elsif clk?event and clk = ?1? then c_st <= n_st; End if; End process; Process (c_st) Begin
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Case c_st is
When st0 => if ina = “00” then n_st <= st0; Else n_st <= st1; End if; Outa <= “0101”;
When st1 => if ina = “00” then n_st <= st1;
Else n_st <= st2; End if; Outa <= “1000”; When st2 => if ina = “11” then n_st <= st0; Else n_st <= st3; End if; Outa <= “1100”; When st3 => if ina = “11” then n_st <= st3; Else n_st <= st0; End if; Outa <= “1101”; When others => n_st <= st0; End case; End process;
End one;
第 8 页 共 8 页 （二）已知一个简单的波形发生器的数字部分系统框图如下图所示
图中lcnt、lrom都是在QuartusII中使用MegaWizard调用的LPM模块，其VHDL描述中Entity部分分别如下： ENTITY lcnt IS PORT ( clock : IN STD_LOGIC ; q : OUT STD_LOGIC_VECTOR (9 DOWNTO 0)); END lcnt;
ENTITY lrom IS PORT ( address : IN STD_LOGIC_VECTOR (9 DOWNTO 0); q : OUT STD_LOGIC_VECTOR (9 DOWNTO 0)); END lrom; 试用VHDL描述该系统的顶层设计（使用例化语句）。（8分） Library ieee;
Use ieee.std_logic_1164.all; Entity mysg is Port (clk : in std_logic; To_da : out std_logic_vector (9 downto 0) ); End mysq;
Architecture one of mysq is Signal addr : std_logic_vector (9 downto 0); Component lcnt Port (clock : in std_logic; Q : out std_logic_vector (9 downto 0) ); End component; Component lrom Port (address : in std_logic_vector (9 downto 0); Q : out std_logic_vector (9 downto 0) ); End component; Begin U1 : lcnt port map (clock => clk, q => addr); U2 : lrom port map (address => addr, q => to_da);
End one;
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