1.设计一个带计数使能、同步复位、带进位输出的增1六位二进制计数器，计数结果由共阴极七段数码管显示。
library ieee;
use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity counter is
port(clk,clk1,en,clr:in std_logic;
ledout:out std_logic_vector(6 downto 0); scanout:out std_logic_vector(1 downto 0); co:out std_logic); end counter;
architecture a of counter is
signal cnt:std_logic_vector(7 downto 0); signal led:std_logic_vector(6 downto 0); signal scan:std_logic:='0';
signal hex:std_logic_vector(3 downto 0); begin
process(clk) begin
if(clk'event and clk='1')then if en='1'then if clr='1'then
cnt<=(others=>'0'); else
if cnt=\ cnt<=\ co<='1'; else
cnt<=cnt+'1'; co<='0'; end if; end if; end if; end if; end process; process(clk1) begin
if clk1'event and clk1='1'then scan<=not scan; end if; end process; ledout<= not led;
scanout<=\
hex<=cnt(7 downto 4) when scan='1'else cnt(3 downto 0);
with hex select
led<=\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \end a;
2、设计一个带计数使能、异步复位、带进位输出的增1二十进制计数器，计数结果由共阴极七段数码管显示。
library ieee;
use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity da is
Port ( clk : in STD_LOGIC; clk1 : in STD_LOGIC; clr : in STD_LOGIC; en : in STD_LOGIC; co : out STD_LOGIC;
ledout : out STD_LOGIC_VECTOR (6 downto 0); sel : out STD_LOGIC_VECTOR (1 downto 0)); end da;
architecture ehavioral of da is
signal cnt:std_logic_vector(7 downto 0):=\ signal led:std_logic_vector(6 downto 0); signal scan:std_logic:='0';
signal hex:std_logic_vector(3 downto 0); begin
process(clk,clr) begin
if clr='1'then
cnt<=(others=>'0');
elsif clk'event and clk='1' then
if en='1'then
if cnt=\ cnt<=\ co<='0';
elsif cnt=\ cnt<=\ co<='1'; else
cnt<=cnt+'1'; co<='0'; end if; end if; end if; end process; process(clk1) begin
if clk1'event and clk1='1'then scan<=not scan; end if; end process;
hex<=cnt(7 downto 4) when scan='1'else cnt(3 downto 0); with hex select
led<=\ \ \ \ \ \ \ \ \
\ \ ledout<= not led; sel<=\end ehavioral;
3、设计一个带计数使能、同步复位、同步装载的可逆七位二进制计数器，计数结果由共阴极七段数码管显示。
library ieee;
use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity counter is
port(clk,clks,clr,en,stld,dir:in std_logic; din:in std_logic_vector(6 downto 0);
ledout:out std_logic_vector(6 downto 0); scanout:out std_logic_wector(1 downto 0); end counter;
architecture a of counter is
signal cnt:std_logic_vector(6 downto 0); signal led:std_logic_vector(6 downto 0); signal scan:std_logic;
signal hex:std_logic_vector(3 downto 0); begin
process(clk,clr) begin
if clk'event and clk='1'then if clr='1' then
cnt<=(others=>'0'); else
if stld='0' then cnt<=din;
elsif en='1' then if dir='1' then
if cnt =”01111111” then cnt <= “00000000”; co<=’1’; else cnt <= cnt + 1; end if; else
if cnt =”00000000” then cnt <= “01111111”; co<=’1’; else cnt <= cnt - 1;
end if; end if; end if; end if; End if;
end process; process(clks) begin
if clks'event and clks='1'then scan<=not scan; end if; end process; ledout<=not led;
scanout<=\
hex<='0'&cnt(6 downto 4) when scan='1' else cnt(3 downto 0); with hex select
led<= \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ End a ;
4、设计一个带计数使能、异步复位、异步装载、可逆计数的通用计数器。计数结果由共阴极七段数码管显示。 library ieee;
use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity counter is
generic(count_value:integer:=9); port(clk,clr,en,load,dir:in std_logic;
data_in:in integer range 0 to count_value; count:out integer range 0 to count_value; ledout:out std_logic_vector(6 downto 0)); end counter;
architecture a of counter is
signal cnt:integer range 0 to count_value; signal led:std_logic_vector(6 downto 0); begin
process(load,clk) begin
if clr='1' then cnt<=0; else
if load='1' then cnt<=data_in; elsif(clk'event and clk='1') then if en='1' then
if dir='1' then
if cnt=count_value then cnt<=0; else
cnt<=cnt+1; end if; else
if cnt=0 then
cnt<=count_value; else cnt<=cnt-1; end if; end if; end if; end if; end if; end process; count<=cnt; ledout<=not led; with cnt select
led<= \ \ \ \ \ \ \ \ \ \ \End a;
5、设计一个具有16分频、8分频、4分频和2分频功能的分频器
library ieee;
use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all;
entity clkdiv is port(clk:in std_logic; clk_div2:out std_logic; clk_div4:out std_logic; clk_div8:out std_logic;
clk_div16:out std_logic); end clkdiv;
architecture rtl of clkdiv is
signal count:std_logic_vector(3 downto 0); begin process(clk) begin
if (clk'event and clk='1') then if(count=\ count<=(others=>'0'); else
count<=count+1; end if; end if; end process; clk_div2<=count(0); clk_div4<=count(1); clk_div8<=count(2); clk_div16<=count(3); end rtl;
6、设计一个正负脉宽相等的通用分频器
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL; ENTITY counter IS
GENERIC( count_value: INTEGER:=15); PORT (clk,clr,en: IN STD_LOGIC; count:OUT STD_LOGIC); END counter;
ARCHITECTURE a OF counter IS
SIGNAL cnt: INTEGER RANGE 0 TO count_value; SIGNAL co: STD_LOGIC; SIGNAL count1:STD_LOGIC; BEGIN
PROCESS (clk,clr) BEGIN IF clr = '1' THEN cnt <= 0; ELSIF (clk'EVENT AND clk = '1') THEN IF en = '1' THEN IF cnt = count_value THEN
cnt <= 0; co<='1'; ELSE
cnt <= cnt + 1; co<='0'; END IF; END IF; END IF; END PROCESS; PROCESS(co ) BEGIN
IF( co'EVENT AND co = '1')THEN count1<=NOT count1; END IF;
count<=count1; END PROCESS; END a;
7、设计一个正负脉宽可控的16分频的分频器
library ieee;
use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity fen_pin is port(clk:in std_logic;
din:in std_logic_vector(1 downto 0); count:out std_logic); end fen_pin;
architecture behave of fen_pin is signal co:std_logic; begin
count<=co; process(clk)
variable cnt:std_logic_vector(3 downto 0); begin
if(clk'event and clk='1')then if(cnt= \cnt:=\co<=not co;
elsif(cnt=din)then co<=not co; cnt:=cnt+'1'; else cnt:=cnt+'1'; end if; end if;
end process;
end behave;
8、根据需要设计一个分频器：可以控制实现四种分频形式：第一种：8分频、第二种：10分频、第三种：15分频、第四种：16分频，其中8分频和16分频为正负脉宽相等的分频器
library ieee;
use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity fenpin is
port(clk:in std_logic;
en:in std_logic_vector(1 downto 0); cout:out std_logic;
ledout:out std_logic_vector(6 downto 0)); end fenpin;
architecture dgnfenpin of fenpin is signal led:std_logic_vector(6 downto 0); signal hex:std_logic_vector(3 downto 0); begin process(clk)
variable cnt:std_logic_vector(3 downto 0); begin
if(clk'event AND clk='1')then if(en=\ if(cnt>=\ cnt:=\ else
cnt:=cnt+'1'; end if; cout<=cnt(2); elsif(en=\ if(cnt>=\ cnt:=\ cout<='1'; else
cnt:=cnt+'1'; cout<='0'; end if; elsif(en=\ if(cnt>=\ cnt:=\ else
cnt:=cnt+'1';cout<='0'; end if; else
if(cnt>=\ cnt:=\ else
cnt:=cnt+'1'; end if; cout<=cnt(3); end if; end if; end process; ledout<=not led; with en select
led<=\ \ \ \ \end dgnfenpin;
9、设计一个M序列发生器，M序列为“11100111”
LIBRARY IEEE;
USE IEEE.STD_logic_1164.all;
USE IEEE.STD_LOGIC_UNSIGNED.ALL; ENTITY SEQ IS
PORT(CLK:IN STD_logic;
FOUT:OUT STD_logic); END SEQ;
ARCHITECTURE BEHAVE OF SEQ IS
SIGNAL CNT:STD_logic_VECTOR(2 DOWNTO 0); BEGIN
PROCESS(CLK) BEGIN
IF CLK'EVENT AND CLK='1' THEN IF CNT=\CNT<=\ELSE
CNT<=CNT+'1'; END IF; END IF;
END PROCESS;
WITH CNT SELECT FOUT<='1' WHEN \'1' WHEN \'1' WHEN \'0' WHEN \'0' WHEN \'1' WHEN \'1' WHEN \'1' when \
'0' WHEN OTHERS; end BEHAVE;
10、设计一个彩灯控制器，彩灯共有21个，每次顺序点亮相邻的3个彩灯，如此循环执行，循环的方向可以控制
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all; entity caideng is
port(clk,reset:in std_logic;
l_r:in std_logic; ----控制循环方向；
output:out std_logic_vector(15 downto 0));---输出 end entity;
architecture art of caideng is
signal q:std_logic_vector(15 downto 0); begin
process(clk,reset,l_r,q) begin
if reset='1' then
q<=\
elsif clk'event and clk='1' then
if l_r='1' then ----表示向右循环； if q=\ q<=\ else q<=q(0)&q(15 downto 1); end if;
else ----向左循环;
if q=\ q<=\ else q<=q(14 downto 0)&q(15);
end if;
end if; end if; output<=q; end process; end art;
11、设计一个具有左移、右移控制，同步并行装载和串行装载的8位串行移位寄存器
library ieee;
use ieee.std_logic_1164.all; entity shifter is port(clr:in std_logic; clk:in std_logic; ser:in std_logic;
clkin:in std_logic; stld:in std_logic;
din:in std_logic_vector(0 to 7); en:in std_logic; qh:out std_logic); end shifter;
architecture rt1 of shifter is
signal reg:std_logic_vector(0 to 7); signal aa:std_logic; begin
process(clk,clr) begin
if clr='1' then reg<=(others=>'0'); aa<=reg(7);
elsif clk'event and clk='1' then if clkin='0' then if stld='0'then reg<=din; else
if en='1' then reg<=ser®(0 to 6); aa<=reg(7);
elsif en='0' then
reg<=reg(1 to 7)&ser;
aa<=reg(0); end if; end if; end if; end if;
end process; qh<=aa; end rt1;
12、设计一个15人表决电路，参加表决者为15人，同意为1，不同意为0，同意者过半则表决通过，绿指示灯亮，表决不通过则红指示灯亮。数码管显示赞成人数。
library ieee;
use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity selector is
port(a:in std_logic_vector(14 downto 0); r,g:out std_logic;
ledout:out std_logic_vector(6 downto 0)); end selector;
architecture rt1 of selector is
signal led:std_logic_vector(6 downto 0); signal count:std_logic_vector(3 downto 0); begin
process(a)
variable cnt:std_logic_vector(3 downto 0); begin
cnt:=\
for i in 0 to 14 loop if a(i)='1' then cnt:=cnt+1; end if; end loop;
if(cnt>=\ g<='1'; r<='0';
elsif(cnt>=\ g<='0'; r<='1'; end if; count<=cnt; end process; ledout<=not led;
with count select
led<=\ \ \ \ \ \ \ \ \ \end rt1;
13、设计一个异步复位，同步并行装载的8位串行左移移位寄存器
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL; ENTITY shifter IS
PORT(clk,clr,ser,stld:IN STD_LOGIC; din: IN STD_LOGIC_VECTOR(0 TO 7) ; qh:OUT STD_LOGIC); END shifter;
ARCHITECTURE rt1 OF shifter IS
SIGNAL reg:STD_LOGIC_VECTOR(0 TO 7); begin
process(clk,clr) begin
if clr='1' then
reg<=(others=>'0');
elsif clk'event and clk='1'then if stld='0'then reg<=din; else
reg<=reg(1 to 7)&ser; end if; end if;
end process; qh<=reg(0); end rt1;
14、有16个开关，编号为0到15，编号0的优先级最高。当某一个拨码开关为1时由共阴极七段数码管显示其编号（可用16进制数显示，亦可用十进制显示）
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL; ENTITY bhxs IS
PORT(INPUT:IN STD_LOGIC_VECTOR(15 DOWNTO 0);
LEDOUT: out STD_LOGIC_VECTOR(6 DOWNTO 0)); END bhxs;
ARCHITECTURE RT1 OF bhxs IS
SIGNAL LED:STD_LOGIC_VECTOR(6 DOWNTO 0); BEGIN
process(INPUT) begin
LEDOUT<= LED; IF(INPUT(0)='1')then LED<=\
ELSIF(INPUT(1)='1')then LED<=\
ELSIF(INPUT(2)='1')then LED<=\
ELSIF(INPUT(3)='1')then LED<=\
ELSIF(INPUT(4)='1')then LED<=\
ELSIF(INPUT(5)='1')then LED<=\
ELSIF(INPUT(6)='1')then LED<=\
ELSIF(INPUT(7)='1')then LED<=\
ELSIF(INPUT(8)='1')then LED<=\
ELSIF(INPUT(9)='1')then LED<=\
ELSIF(INPUT(10)='1')then LED<=\
ELSIF(INPUT(11)='1')then LED<=\
ELSIF(INPUT(12)='1')then LED<=\
ELSIF(INPUT(13)='1')then LED<=\
ELSIF(INPUT(14)='1')then LED<=\
ELSIF(INPUT(15)='1')then LED<=\ END IF;
END PROCESS; END RT1;
15、设计一个全自动洗衣机水位控制器。要求：当水位超过某一上限值时，停
止加水，启动洗衣机；当水位低于某一下限值时，加水，停止洗衣机；否则启动洗衣机，停止加水。
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL; ENTITY xiyiji IS
PORT(clk,water_high,water_low:IN STD_LOGIC; jiashui,qitong:OUT STD_LOGIC); END xiyiji;
ARCHITECTURE style OF xiyiji IS
TYPE state IS(just_right,too_high,too_low); SIGNAL now_state,next_state:state; BEGIN
PROCESS(now_state,water_high,water_low) BEGIN
CASE now_state IS
WHEN just_right=>jiashui<='0';qitong<='1'; IF water_low='1' THEN next_state<=too_low;
ELSIF water_high='1' THEN next_state<=too_high; ELSE next_state<=just_right; END IF;
WHEN too_low=>jiashui<='1';qitong<='0';
IF water_low='1' THEN next_state<=too_low;
ELSIF water_high='1' THEN next_state<=too_high; ELSE next_state<=just_right; END IF;
WHEN too_high=>jiashui<='0';qitong<='1'; IF water_low='1' THEN next_state<=too_low;
ELSIF water_high='1' THEN next_state<=too_high; ELSE next_state<=just_right; END IF; END CASE; END PROCESS; PROCESS(clk) BEGIN
IF(clk'event AND clk='1')THEN now_state<=next_state; END IF;
END PROCESS; END style;
16、根据真值表设计一位全加器，然后用结构的描述方法设计一个6位加法器。 library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
ENTITY full_adder IS
PORT(a,b,cin:IN STD_LOGIC; s,co:OUT STD_LOGIC); END full_adder;
ARCHITECTURE full_1 of full_adder is
SIGNAL comb:STD_LOGIC_VECTOR(2 downto 0); BEGIN
comb<=a&b&cin; PROCESS(comb) BEGIN
IF(comb=\ s<='0';co<='0';
elsif(comb=\ s<='1';co<='0'; elsif(comb=\ s<='1';co<='0';
elsif(comb=\ s<='1';co<='0';
elsif(comb=\s<='0';co<='1'; elsif(comb=\s<='0';co<='1';
elsif(comb=\s<='0';co<='1'; else
s<='1';co<='1'; end if;
end process; end full_1;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL; entity full_adder5 is
port( clk: in std_logic; cin:in std_logic;
x,y:in std_logic_vector(5 downto 0);
ledout: out std_logic_vector(6 downto 0); scan_out: out std_logic_vector(1 downto 0); co:out std_logic); end full_adder6;
architecture Behavioral of full_adder6 is component full_adder port(a,b,cin:in std_logic; s,co:out std_logic); end component;
signal z:std_logic_vector(4 downto 0); signal sum: std_logic_vector(5 downto 0); signal scan: std_logic_vector(1 downto 0); signal hex: std_logic_vector(3 downto 0); signal led: std_logic_vector(6 downto 0); begin
uo:full_adder port map(x(0),y(0),cin,sum(0),z(0)); u1:full_adder port map(x(1),y(1),z(0),sum(1),z(1)); u2:full_adder port map(x(2),y(2),z(1),sum(2),z(2)); u3:full_adder port map(x(3),y(3),z(2),sum(3),z(3)); u4:full_adder port map(x(4),y(4),z(3),sum(4),z(4)); u5:full_adder port map(x(5),y(5),z(4),sum(5),co); scan_out<=scan; ledout<=not led; process(clk) begin
if (clk'event and clk='1') then if scan=\ scan<=\
else scan<=\ end if; end if; end process;
hex<=”00”&sum( downto 4)when scan=\led<= \ \ \
\ \ --4 \ --5 \ --6 \ --7 \ --8 \ --9 \ --A \ --B \ --C \ --D \ \ --F \
end Behavioral;
17、设计4位二进制数到BCD码（8421码）的转换器。结果由共阴极数码管显示。
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL; use ieee.std_logic_unsigned.all; ENTITY bcd IS PORT(
scanclk:IN STD_LOGIC;
din:IN STD_LOGIC_VECTOR(3 DOWNTO 0);
ledout:OUT STD_LOGIC_VECTOR(6 DOWNTO 0); scanout:out integer range 0 to 1 );
END bcd;
ARCHITECTURE a OF bcd IS
signal yh,yl,hex:integer range 0 to 9; signal scan:integer range 0 to 1;
signal led:std_logic_vector(6 downto 0); signal y:integer range 0 to 15; BEGIN
y<=conv_integer(din);
yh<=1 when y>=10 and y<16 else 0; yl<=y when y>=0 and y<10 else (y-10)when y>=10 and y<16 else 0; process(scanclk)
begin
if(scanclk'event and scanclk='1')then if scan=1 then scan<=0; else
scan<=1; end if; end if; end process;
with scan select hex<=yh when 1, yl when others; ledout<=not led; scanout<=scan; with hex select
led<=\ \ \ \ \ \ \ \ \ \END a;
BCD码显示（5个数码管） LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL; use ieee.std_logic_unsigned.all; ENTITY bcd IS PORT(
scanclk:IN STD_LOGIC;
din:IN STD_LOGIC_VECTOR(3 DOWNTO 0);
ledout:OUT STD_LOGIC_VECTOR(6 DOWNTO 0); scanout:out integer range 0 to 4 );
END bcd;
ARCHITECTURE a OF bcd IS signal scan:integer range 0 to 4;
signal led:std_logic_vector(6 downto 0); signal hex,yh:std_logic;
signal yl:std_logic_vector(3 downto 0);
END IF; END IF;
END PROCESS; LED<=REG; END A;
32、用状态机设计方法设计一个汽车尾灯控制器。该控制器共有4种状态：状态A代表正常直行或静止；状态B代表左转弯；状态C代表右转弯；状态D代表刹车；三个控制信号：LH左转弯控制；RH右转弯控制；JWH刹车控制。两个输出控制：LD点亮左尾灯控制输出；RD点亮右尾灯控制输出。其状态转移
LH=’1’ RH=’0’ JMH=’0’ LH=’0’ RH=’0’ JMH=’0’ LH=’0’ RH=’1’ JMH=’0’ LD=’1’ RD=’0’ LH=’1’ RH=’0’ JMH=’0’ B A LD=’0’ C LD=’0’ RD=’1’ LH=’0’ RH=’1’ JMH=’0’ LH=’0’ LH=’0’ RD=’0’ RH=’0’ RH=’0’ JMH=’0’ JMH=’0’ LH=’0’ LH=’0’ RH=’0’ RH=’0’ JMH=’1’ JMH=’0’ LD=’1’ RD=’1’ D LH=’0’ RH=’0’ JMH=’1’ 图如下：
ENTITY exam35 IS
PORT (CLK,JMH,LH,RH,RESET: IN std_logic; LD,RD : OUT std_logic); END exam35;
ARCHITECTURE BEHAVIOR OF exam35 IS
TYPE type_sreg IS (right,STOP,TURNL,TURNR); SIGNAL sreg, next_sreg : type_sreg;
BEGIN
PROCESS (sreg,JMH,LH,RH) BEGIN
CASE sreg IS WHEN right =>LD<='0';RD<='0'; IF ( RH='1' AND LH='0' AND JMH='0' ) THEN next_sreg<=TURNR;
END IF;
IF ( LH='1' AND RH='0' AND JMH='0' ) THEN next_sreg<=TURNL; END IF;
IF ( LH='0' AND RH='0' AND JMH='1' ) THEN next_sreg<=STOP; END IF;
IF ( LH='0' AND RH='0' AND JMH='0' ) THEN next_sreg<=right;
END IF;
WHEN STOP =>LD<='1';RD<='1'; IF ( LH='1' ) OR ( RH='1' ) THEN
next_sreg<=STOP; END IF;
IF ( LH='0' AND RH='0' AND JMH='1' ) THEN next_sreg<=STOP;
END IF; IF ( LH='0' AND RH='0' AND JMH='0' ) THEN next_sreg<=right; END IF;
WHEN TURNL =>LD<='1';RD<='0'; IF ( RH='1' ) OR ( JMH='1' ) THEN next_sreg<=TURNL; END IF;
IF ( LH='1' AND RH='0' AND JMH='0' ) THEN next_sreg<=TURNL; END IF;
IF ( LH='0' AND RH='0' AND JMH='0' ) THEN next_sreg<=right; END IF;
WHEN TURNR =>LD<='0';RD<='1';
IF ( LH='1' ) OR ( JMH='1' ) THEN next_sreg<=TURNR; END IF;
IF ( LH='0' AND RH='1' AND JMH='0' ) THEN next_sreg<=TURNR; END IF;
IF ( LH='0' AND RH='0' AND JMH='0' ) THEN next_sreg<=right;
END IF; END CASE;
END PROCESS;
PROCESS (CLK, reset) BEGIN IF ( RESET='1' ) THEN sreg<=STOP; elsif CLK='1' AND CLK'event THEN
sreg <= next_sreg; END IF; END PROCESS; END BEHAVIOR;
33、某医院1到8号病房共8间，每室设有呼叫按钮，同时护士值班室内有一个共阴极的七段数码管显示病房号；当多个病房同时有按钮按下时，病房号小的先显示。
library ieee;
use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity hujiao is
port(input:in std_logic_vector(8 downto 1); ledout:out std_logic_vector(6 downto 0)); end hujiao;
architecture a of hujiao is
signal cnt: std_logic_vector(3 downto 0); signal b:std_logic_vector(6 downto 0);
begin
process(input) begin
if(input(1)='1')then cnt<=\
elsif(input(2)='1')then cnt<=\
elsif(input(3)='1')then cnt<=\
elsif(input(4)='1')then cnt<=\
elsif(input(5)='1')then cnt<=\
elsif(input(6)='1')then cnt<=\
elsif(input(7)='1')then cnt<=\
elsif(input(8)='1')then cnt<=\ else
cnt<=\ end if; end process; with cnt select
b<=\ \ \ \ \ \ \ \ \ledout<=not b; end a;