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5.7 位同步程序与仿真图
library IEEE; --相位比较模块 use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL; entity phase_compare is
port(Reset :in std_logic; Clk_Est :in std_logic; Date_In :in std_logic;
Phase_Error :out std_logic_vector(1 downto 0) );
end phase_compare;
architecture rtl of phase_compare is
signal Temp_SampleA :std_logic; signal Temp_SampleB :std_logic; signal Temp_SampleC :std_logic;
begin
process(Reset,Clk_Est) begin
if(Reset='0')then
Temp_SampleA<='0'; Temp_SampleC<='0';
elsif(Clk_Est'event and Clk_Est='0')then
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Temp_SampleA<=Temp_SampleC; Temp_SampleC<=Date_in; end if;
end process;
process(Reset,Clk_Est) begin
if(Reset='0')then
Temp_SampleB <='0';
elsif(Clk_Est'event and Clk_Est='1')then Temp_SampleB<=Date_in; end if;
end process;
process (Reset,CLK_Est) begin
if(Reset='0')then
Phase_Error<=\
elsif(Clk_Est'event and Clk_Est='0')then
Phase_Error(0)<=Temp_SampleA xor Temp_SampleC; Phase_Error(1)<=Temp_SampleB xor Temp_SampleC; end if;
end process;
end rtl;
library IEEE; --数字滤波模块IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity loop_filter is generic(M:integer);
port(Reset :in std_logic; Clk :in std_logic; Clk_Est :in std_logic;
Phase_Error :in std_logic_vector(1 downto 0); insert_signal :out std_logic; reduce_signal :out std_logic
);
end loop_filter;
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use
architecture rtl of loop_filter is
signal value_lever :integer range 0 to 255; signal count_sample :integer range 0 to 7;
begin
process(Reset,Clk_Est) begin
if(Reset = '0') then
Value_Lever <= M/2-1;
elsif(Clk_Est'event and Clk_Est='1') then
if((Value_Lever = 0) or (Value_Lever = M-1)) then Value_Lever <= M/2-1; else
case Phase_Error is when \ Value_Lever <= Value_Lever - 1; when \ Value_Lever <= Value_Lever + 1; when others => end case; end if; end if;
end process;
process(Reset, Clk) begin
if(Reset = '0') then
Count_sample <= 0;
elsif(Clk'event and CLk = '1') then Count_sample <= Count_sample+1; end if;
end process;
process(Reset, Clk) begin
if(Reset = '0') then
insert_signal <= '0'; reduce_signal <= '0';
elsif(Clk'event and CLk = '0') then
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if(Count_sample=0)then if(value_lever=0)then reduce_signal <= '1'; elsif(value_lever=M-1)then insert_signal <= '1'; end if; else
insert_signal <= '0'; reduce_signal <= '0'; end if; end if;
end process;
end rtl;
library IEEE; --可控分频模块 use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity digital_co is
port(Reset :in std_logic; Clk :in std_logic; Clk_Est :buffer std_logic; insert_signal :in std_logic; reduce_signal :in std_logic );
end digital_co;
architecture rtl of digital_co is
signal Count_Control :integer range 0 to 7;
begin
process(Reset, Clk) begin
if(Reset = '0') then
Count_Control <= 0;
elsif(Clk'event and CLk = '1') then if(Insert_Signal = '1') then
Count_Control <= Count_Control; elsif(Reduce_Signal = '1') then
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Count_Control <= Count_Control + 2; else
Count_Control <= Count_Control + 1; end if; end if;
end process;
process(Reset, Clk) begin
if(Reset = '0') then clk_est <= '0';
elsif(Clk'event and CLk = '0') then if(Count_Control = 7) then clk_est <=not clk_est;
end if; end if;
end process;
end rtl;
library IEEE; --顶层设计模块 use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity digital_pll is
port(Reset :in std_logic; Clk :in std_logic; Date_In :in std_logic;
Clk_estimate :out std_logic; data_out :out std_logic );
end digital_pll;
architecture rtl of digital_pll is
component phase_compare port(Reset :in std_logic; Clk_Est :in std_logic; Date_In :in std_logic;
Phase_Error :out std_logic_vector(1 downto 0) );
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