数字电路课程设计报告
3、递增锯齿波模块
（1）程序 library ieee;
use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; use ieee.std_logic_arith.all; entity juchizeng is port (clk:in std_logic; reset:in std_logic;
dout:out std_logic_vector(7 downto 0)); end juchizeng;
architecture three of juchizeng is signal q:std_logic_vector(7 downto 0); begin
process(clk,reset,q) begin
if reset='1' then q<=\else
if clk='1' and clk'event then if q<255 then q<=q+1; else q<=\end if; end if; end if;
end process; dout<=q; end three;
（2）波形
当计数值为255时，清零，再加1计数 （3）分析
若reset为‘1’，表示复位有效，对波形复位，否则判断脉冲信号输入是否为上升沿。如果为上升沿脉冲，将进行计数。在进行计数时，先判断当前计数值是否为“11111111”；若是则将计数值清零，否则进行加1计数。
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数字电路课程设计报告
4、正弦波模块
（1）程序 library ieee;
use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; use ieee.std_logic_arith.all; entity sine is
port( clk:in std_logic; reset:in std_logic;
dout:out std_logic_vector(7 downto 0)); end sine;
architecture four of sine is signal cnt_val:integer; begin
u1:process(clk,reset)
variable cnt: integer range 0 to 63; begin
if reset='1' then cnt:=0;
elsif clk'event and clk='1' then if cnt=63 then cnt:=0; else
cnt:=cnt+1; end if; end if;
cnt_val<=cnt; end process u1;
u2:process(cnt_val) begin
case cnt_val is
when 0=>dout<=\when 1=>dout<=\when 2=>dout<=\when 3=>dout<=\when 4=>dout<=\when 5=>dout<=\when 6=>dout<=\when 7=>dout<=\when 8=>dout<=\when 9=>dout<=\
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数字电路课程设计报告
when 10=>dout<=\when 11=>dout<=\when 12=>dout<=\when 13=>dout<=\when 14=>dout<=\when 15=>dout<=\when 16=>dout<=\when 17=>dout<=\when 18=>dout<=\when 19=>dout<=\when 20=>dout<=\when 21=>dout<=\when 22=>dout<=\when 23=>dout<=\when 24=>dout<=\when 25=>dout<=\when 26=>dout<=\when 27=>dout<=\when 28=>dout<=\when 29=>dout<=\when 30=>dout<=\when 31=>dout<=\when 32=>dout<=\when 33=>dout<=\when 34=>dout<=\when 35=>dout<=\when 36=>dout<=\when 37=>dout<=\when 38=>dout<=\when 39=>dout<=\when 40=>dout<=\when 41=>dout<=\when 42=>dout<=\when 43=>dout<=\when 44=>dout<=\when 45=>dout<=\when 46=>dout<=\when 47=>dout<=\when 48=>dout<=\when 49=>dout<=\when 50=>dout<=\when 51=>dout<=\
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数字电路课程设计报告
when 52=>dout<=\when 53=>dout<=\when 54=>dout<=\when 55=>dout<=\when 56=>dout<=\when 57=>dout<=\when 58=>dout<=\when 59=>dout<=\when 60=>dout<=\when 61=>dout<=\when 62=>dout<=\when 63=>dout<=\when others=>null; end case;
end process u2; end four;
（2）波形
（3）分析
若reset为‘1’时，表示复位有效，对波形抚慰，否则判断脉冲信号输入是否为上升沿，如果为上升沿脉冲，将进行采样次数的计数。在进行计数时，先判断当前计数值是否为63，若否（即采样了64次），将计数值置为‘0’；否则进行加1计数。
5、方波模块
（1）程序
library ieee;
use ieee.std_logic_1164.all; entity square is
port(clk,clr:in std_logic;
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数字电路课程设计报告
q:out integer range 0 to 255); end square;
architecture five of square is signal a:bit; begin
process(clk,clr)
variable cnt:integer; begin
if (clr='1') then a<='0';
elsif (clk'event and clk='1' )then if cnt<63 then
cnt:=cnt+1; else
cnt:=0; a<= not a; end if; end if;
end process; process(clk,a) begin
if(clk'event and clk='1') then if (a='1') then q<=255; else q<=0; end if; end if; end process; end five;
（2）波形
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