件的path要特别留意matching,而这点,要看设计者是用那一种PFD电路,若没有特别交待,那layout人员是不会特别留心的
再来则是Voltage Control Oscillator(VCO),这是整个PLL电路中最难画的地方,同时也是最需要特别留意且小心的电路,一般设计者均会用differential circuit,所以,元件的对称要非常小心,同时,它是ring的形式,故而stage1到stage2的摆放位置与拉线要特别留意,同时要注意跨线与VDD和GND的跑线,因为一个不小心就会让VCO的jitter变大,同时也会造成phase-to-phase的误差变大,所以,VCO电路是最难画也需最小心的电路,建议在画这块电路时,一定要请设计者说明他想要layout怎么摆放各个元件及拉线,通常,我会将这块电路放在LPF的上方且紧靠在最右边的地方,再者,因为这块电路不算小,所以,VCO的layout的高度大概是PFD +CP的layout高度
最后一块电路则是post-divider,我通常是放在PLL的最上方,它是数位电路,没什么需要特别留意的地方,不过,有时候我们会把pre-divider和post-divider都放在同一块
最后,PLL的信号连线顺序是由pre-divider进去,然后接到PFD,再到CP,再到LPF,再到VCO,最后到post-divider,所以,我的layout摆放位置也是依照此一顺序来走而不会有各个子电路交错的问题,所以,这些都是原设计者要交待layout人员的地方。
模拟设计的基本考虑
1. Minimum channel length of the transistor should be four to five times the minimum feature size of the process. We do it, to make the lambda of the transistor low i.e. the rate of change of Id w.r.t t
o Vds is low.
晶体管最小沟长为工艺最小特征尺寸的4-5倍，用来减小沟长调制效应
2. Present art of analog design still uses the transistor in the saturation region.So one should always keep Vgs of the Transistor 30% above the Vt.
目前模拟设计仍然是使晶体管工作在饱和区，故应使Vgs大于Vt约30%
3. One should always split the big transistor into small transistors having width or length feature size
应把大管分成小晶体管，使其宽/长特征尺寸<或=15um
4. W/L Ratio of transistors of the mirror circuit should be less than or equal to 5, to ensure the proper matching of the transistors in the layout. Otherwise, it results to the Systamatic Offset in the circuit. 电流镜电路的晶体管的w/l比应小于或等于5，以保证较好的Matching,否则会有系统失调
5. One should make all the required pins in the schmetic before generating the layout view. Because it’s diffcult to add a pin in the layout view. All IO pins should be a metal2 pins whereas Vdd and Ground should be metal1 pins
在电路中画出所有的管脚（pin），之后才作layout。因为在layout中增加一个pin是比较困难的。所有的IO pin应该用metal2 pin，Vdd和GND用metal1 pin
6. One should first simulate the circuit with the typical model parameters of the devices. Since Vt of the trasistor can be anything between Vt(Typical) -/+ 20%. So we check our circuit for the extreme cases i.e. Vt+20%, Vt-20%. A transistor having Vt-20% is called a fast transistor and transistor having Vt+20% is called slow transistor. It’s just a way to differentiate them. So with these fast and slow transistor models we make four combination called nfpf, nfps, nspf, nsps, which are known as process corners. Now, once we are satisfied with the circuit performance with typical models than we check it in different process corners, to take the process variation into account. Vt is just one example of the process variation there are others parameter too.
首先先用tt做电路仿真。考虑Vt有+20% (slow)和-20% (fast),需要对工艺角考虑，FF，SS，FS，SF。除Vt，其他工艺参数也会有变化
7. Its thumb rule that poly resistance has a 20% process variation whereas well resistance has got 10%. But the poly resistance has got lower temperature coefficent and lower Sheet Resistance than well resistance So we choose the resistance type depending upon the requirments. Poly Capacitance has got a process variation of 10%.
多晶硅电阻大约有20%的工艺变化，而阱区电阻变化约为10%。但多晶硅电阻有较低的温度系数和低的方块电阻，应根据需要来选择电阻。多晶硅电容约有10%工艺变化
8. One should also check the circuit performance with the temperature variation. We usuly do it for the range of -40C to 85C.
需考虑温度变化对电路性能的影响，通常在-40C到85C范围
9. One should take the parasitic capacitance into account wherever one is making an overlap with metal layers or wells.
有覆盖金属层或阱区时，须考虑寄生电容
10. In Layout, all transistors should be placed in one direction, to provide the same environment to all the transistors.
Layout中，所有晶体管统一摆放方向，使有相同的环境
11. One should place all transistor in layout with a due care to the pin position before start routing them.
在对晶体管布局布线之前，考虑Pin的位置
12. One should always use the Metal 1 for horizontal routing and Metal 2 for the vertical routing as far as possible.
尽量使用metal1横向布线，metal纵向布线
13. One should never use POLY as routing layer when the interconnects carries a current. One can have a short gate connection using poly.
在互连用来传送电流时，不要用Poly来做互连。可以用poly做短的栅连接。
14. One should try to avoid running metal over poly gate. As this cause to increase in parasitic capacitance.
避免金属在多晶硅栅上走线，会增加寄生电容
15. Current in all the transistor and resistor part should flow in the same direction 所有晶体管和电阻有相同的电流走向
16. One should do the Power(Vdd & Gnd) routing in top layer metal (metal5 only). Because Top layer metals are usually thicker and wider and so has low resistance.
在最上层金属做电源（Vdd和GND）布线。因为最上层金属通常更厚、更宽，因而电阻较小
17. One should always merge drain and source of transistor (of same type) connected together. merge连接的Source和Drain
18. To minimize the process variation in the Resistor value one should always take the resistor’s width three to four times of the default value. we do it to decrease the value of differential of R(L)
为减小工艺变化对电阻影响，应使电阻的宽度为默认值的3-4倍
19. One should cover the resistance with metal layer, to avoid the damaged during the wafer level testing.
用金属覆盖电阻，避免wafer级测试时的损伤
20. One should always make a Common Centroid structure for the matched transistor in the layout. Each differential pair transistor should be divide into four transistors and should be placed in two rows common centroid structure.
One may use the the linear common centroid structure for the current mirror circuit. 对匹配的晶体管用共中心的结构
差分对管，分割为4管，2*2排列，共中心 对电流镜，可用线形共中心
21. It’s advisiable to put a dummy layers around the resistance and the capacitance to avoid the erosion at the time of etching. 建议在电阻和电容周围作dummy
22. One should always have a Guard Ring arround the differential pair. 在差分对周围作保护环
23. Always put a Guard Ring arround the N-well and P-well. 在N阱和P阱作保护环半导体
24. Thumb rule for the metal current density is 0.8mA/um. It’s larger for the top most metal layer. 金属电流密度0.8mA/um，最上层金属可以更大
25. To avoid the Latchup, one should always make the PN junction reverse biased i.e. In NWELL should be connected to positive power supply (Vdd) and PWELL should be connected to negative power supply (Gnd). Designers do it to make the leakage current small.
为避免Latchup，应使PN结反偏，如N-Well应连到正电源，P-Well应连到负电源。这样可减小漏电
26. It’s always a good practice to use a infotext layer to put the name of the device on the top of it in layout and have a netname for every nets in schematic. Designer should put the pin name on the top of the pin with same metaltxt layer because hercuels takes the netname from metaltxt only whereas Diva takes from the pin-name.
在layout中用infotext标明器件名称，在schematic中标明net。用相同的metaltxt层标明pin 27. Cadence SPICE simulator take vdd! & gnd! as a global Vdd and Gnd net i.e. any net ending with \
Cadence 模拟工具对以'!'结尾的net认为全局net
28. Transistor Equation: Id=(beta/2)*square(Vgs-Vt)
基本晶体管方程Id=(beta/2)*square(Vgs-Vt)
布局优先还是连线优先
手工画图的习惯做法是先把要用到的cell摆上去再说，然后再考虑连线问题。比如，想把一个模块画成
方块形状，则在画图的初期，把要用到的cell全部摆上去，根据各个管子的形状，摆成一个粗略的方块形，然后再加guard ring，再连线。这样的做法一个大好处就是省事，不管是什么模块，按这一套流程走下来，总能把它布好，但也有弊端。
如果按上述方法布好了图，在连线的时候，发现模块内部需要连到外面的管子被放到了模块的另一端，而相反的一端也有同样的情况，这样连线的时候难免要扯东扯西，造成连线复杂，工作量加大。同时，上述做法在信号的干扰和屏蔽方面完全没有考虑，只考虑了形状因素，这对于敏感电路是很糟糕的。因此，在布局比较精密的电路时，可考虑优先连线，后考虑布局，这样，即使布出来的版图形状上抑合不好，甚至开天窗，却可以减少连线数量与信号串扰，是一个很好的布图思路。
总的说来，画模拟版图的时候还是要根据电路功能来布图，要求不高的部分，优先考虑布局，对于有对称性要求，信号屏蔽要求，寄生参数大小有要求等的比较苛刻的电路，优先考虑这些因素是比较稳妥的做法。
关于天线效应
by yw
一条条长长的金属线或者多晶硅(polysilicon)等导体，就象是一根根天线，当有游离的电荷时，这些“天线”便会将它们收集起来，天线越长，收集的电荷也就越多，当电荷足够多时，就会放电。
IC现代工艺中经常使用的一种方法是离子刻蚀（plasma etching），这种方法就是将物质高度电离并保持一定的能量，然后将这种物质刻蚀在晶圆上，从而形成某一层。理论上，打入晶圆的离子总的对外电性应该是呈现中性的，也就是说正离子和负离子是成对出现，但在实际中，打入晶圆的离子并不成对，这样，就产生了游离电荷。另外，离子注入（ion implanting）也可能导致电荷的聚集。可见，这种由工艺带来的影响我们是无法彻底消除的，但是，这种影响却是可以尽量减小的。
在CMOS工艺中，P型衬底是要接地的，如果这些收集了电荷的导体和衬底间有电气通路的话，那么这些电荷就会跑到衬底上去，将不会造成什么影响；如果这条通路不存在，这些电荷还是要放掉的，那么，在哪放电就会对哪里造成不可挽回的后果，一般来讲，最容易遭到伤害的地方就是栅氧化层。
通常情况下，我们用“天线比率”（“antenna ratio”）来衡量一颗芯片能发生天线效应的几率。“天线比率”的定义是：构成所谓“天线”的导体（一般是金属）的面积与所相连的栅氧化层面积的比率。随着工艺技术的发展，栅的尺寸越来越小，金属的层数越来越多，发生天线效应的可能性就越大，所以，在0.4um/DMSP/TMSP以上工艺，我们一般不大会考虑天线效应。而采用0.4um以下的工艺就不得不考虑这个问题了。
可通过插入二极管的方法来解决天线效应，这样当金属收集到电荷以后就通过二极管来放电，避免了对栅极的击穿。
QUESTION:为什么跳到更高层的线能避免ANTENNA？？？？