clear: in std_logic; --BTN0--- 复位 -------------------------------------------------------------------
mode: in std_logic ); end entity;
architecture a of dadishu is
--------------------------------------------------------------------------------------------------------- TYPE matrix_index is array (29 downto 0) of std_logic_vector(15 downto 0); constant dishu : matrix_index:=( x\002\
x\
x\ ); signal cnt: integer range 0 to 10000;
signal cnt2: integer range 0 to 50000000; signal clk_tmp : std_logic;
signal st1: std_logic_vector(7 downto 0); --点阵-- signal data: std_logic_vector(7 downto 0); signal ling: std_logic_vector(1 downto 0); signal change: integer range 0 to 29;
signal k: std_logic_vector(15 downto 0):=x\signal red: std_logic_vector(7 downto 0); signal location: std_logic_vector(7 downto 0);
----------------------------------------------------------------------------------------------------------- signal scanand:std_logic_vector(7 downto 0); signal col: std_logic_vector(3 downto 0); signal cntscan:integer range 0 to 3; signal clk_tmp1:std_logic; signal key: std_logic_vector(15 downto 0):=x\ --jianpan--
signal counter1:integer range 0 to 3;
signal counter2:integer range 0 to 50000; signal n: std_logic_vector(15 downto 0);
----------------------------------------------------------------------------------- signal co: std_logic_vector(6 downto 0); signal co1: std_logic_vector(6 downto 0); signal co2: std_logic_vector(6 downto 0);
signal co3: std_logic_vector(6 downto 0); --记分
signal co4: std_logic_vector(6 downto 0); signal cat: std_logic_vector(5 downto 0); signal up: integer range 0 to 1:=0;
signal counter3:integer range 0 to 25000000;
---------------------------------------------------------------------------- signal i: integer range 0 to 20; signal j: integer range 0 to 60; signal vx: integer range 0 to 2;
signal stop: integer range 0 to 1 :=0; -- game over ------------------------------------------------------------------------------- signal fuwei: integer range 0 to 1:=0; --复位 begin
ling<=\
--------------------------------------------------- dianzhen process(clk,rst) begin if rising_edge(clk) and rst='0'then if cnt=10000 then cnt<=0; clk_tmp<= not clk_tmp; else cnt<=cnt+1; end if; end if; end process;
process(clk_tmp1,up,rst,fuwei)
variable count9:integer range 0 to 1000 :=0; begin
if falling_edge(clk_tmp1) and fuwei=1 then change<=29;
elsif falling_edge(clk_tmp1) and fuwei=0 then if up=1 then count9:=0; if change=0 then change<=29; else change<=change-1; end if; elsif up=0 then if count9=1000 then count9:=0; if change=0 then change<=29; else change<=change-1; end if;
else count9:=count9+1; end if; end if; case change is when 29=>k<=dishu(29); when 28=>k<=dishu(28); when 27=>k<=dishu(27); when 26=>k<=dishu(26); -- 随机 when 25=>k<=dishu(25); when 24=>k<=dishu(24); when 23=>k<=dishu(23); when 22=>k<=dishu(22); when 21=>k<=dishu(21); when 20=>k<=dishu(20); when 19=>k<=dishu(19); when 18=>k<=dishu(18); when 17=>k<=dishu(17); when 16=>k<=dishu(16); when 15=>k<=dishu(15); when 14=>k<=dishu(14); when 13=>k<=dishu(13); when 12=>k<=dishu(12); when 11=>k<=dishu(11); when 10=>k<=dishu(10); when 9=>k<=dishu(9); when 8=>k<=dishu(8); when 7=>k<=dishu(7); when 6=>k<=dishu(6); when 5=>k<=dishu(5); when 4=>k<=dishu(4); when 3=>k<=dishu(3); when 2=>k<=dishu(2); when 1=>k<=dishu(1); when 0=>k<=dishu(0); end case; end if;
end process;
process(clk_tmp,rst) begin
if rising_edge(clk_tmp) and rst='0' then
if (vx=2) then if st1=\ st1<=\ elsif st1=\ st1<=\12)&\ elsif st1=\ st1<=\8)&\ elsif st1=\ st1<=\data<='1'&\downto 0);red<='0'&k(7 downto 4)&\ elsif st1=\ st1<=\data<='1'&\downto 0);red<='0'&k(3 downto 0)&\ elsif st1=\ st1<=\ elsif st1=\ st1<=\ elsif st1=\ st1<=\ end if; elsif (vx=1) then if st1=\ st1<=\ elsif st1=\ st1<=\ elsif st1=\ st1<=\ elsif st1=\ st1<=\ elsif st1=\ st1<=\ elsif st1=\ st1<=\ elsif st1=\ st1<=\ elsif st1=\ st1<=\ end if; elsif (vx=0) then if st1=\ st1<=\ elsif st1=\
st1<=\ elsif st1=\ st1<=\ elsif st1=\ st1<=\ elsif st1=\ st1<=\ elsif st1=\ st1<=\ elsif st1=\ st1<=\ elsif st1=\ st1<=\ end if; end if; end if;
end process; row<=st1; colg<=data; colr<=red;
----------------------------------------------------------------------------------------------------键盘 process(clk,rst) begin if rising_edge(clk) and rst='0' then if counter2=50000 then counter2<=0; clk_tmp1<= not clk_tmp1; else counter2<=counter2+1; end if; end if; end process;
process(clk_tmp1,rst) begin
if rising_edge(clk_tmp1) and rst='0' then if cntscan=3 then cntscan<=0; else
cntscan<=cntscan+1; end if;
case cntscan is when 0 =>col<=\