ENTITY muxA IS
PORT(a: IN STD_LOGIC_vector(3 downto 0);
b:out STD_LOGIC_vector(3 downto 0); INDEX :OUTSTD_LOGIC_vector(3 downto 0); Q1:INSTD_LOGIC_vector(3 downto 0); Q2:INSTD_LOGIC_vector(3 downto 0); Q3:INSTD_LOGIC_vector(3 downto 0); Q4:INSTD_LOGIC_vector(3 downto 0));
END muxA;
ARCHITECTURE a OF muxA IS BEGIN
PROCESS (a,Q1,Q2,Q3,Q4) BEGIN
CASE a IS
WHEN \ b<=\ INDEX<=Q1; WHEN \ b<=\ INDEX<=Q2; WHEN \ b<=\ INDEX<=Q3; WHEN \ b<=\ INDEX<=Q4; WHEN OTHERS => null;
END CASE;
END PROCESS;
END a;
创建符号：（如图3）
图3
3、TONETABA模块：
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL; ENTITY TONETABA IS
PORT(
INDEX
: IN STD_LOGIC_vector(3 downto 0);
CODE : OUT STD_LOGIC_vector(3 downto 0); HIGH : OUT STD_LOGIC;
TONE : OUT STD_LOGIC_vector(10 downto 0));
END TONETABA;
ARCHITECTURE a OF TONETABA IS BEGIN
SEARCH:
PROCESS (INDEX) BEGIN
CASE INDEX IS
WHEN \=> TONE <= \\<=
'0';--2047
WHEN \=> TONE <= \\<=
'0';--773
WHEN \=> TONE <= \\<=
'0';--912
WHEN \=> TONE <= \\<=
'0';--1036
WHEN \=> TONE <= \\<=
'0';--1197
WHEN \=> TONE <= \\<=
'0';--1290
WHEN \=> TONE <= \\<=
'0';--1372
WHEN \=> TONE <= \\<=
'1';--1410
WHEN \=> TONE <= \\<=
'1';--1480
WHEN \=> TONE <= \\<=
'1';--1542
WHEN \=> TONE <= \\<=
'1';--1622
WHEN \=> TONE <= \\<=
'1';--1668
WHEN \=> TONE <= \\<=
'1';--1728
WHEN OTHERS => NULL;
END CASE;
END PROCESS;
END a;
创建符号：（如图4）
图4
4、SPEAKERA模块：
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL; useieee.std_logic_unsigned.all; ENTITY SPEAKERA IS
PORT(
CLK : IN STD_LOGIC;
TONE : IN STD_LOGIC_vector(10 downto 0); SPKS : OUT STD_LOGIC);
END SPEAKERA;
ARCHITECTURE a OF SPEAKERA IS
SIGNAL PRECLK : STD_LOGIC; SIGNAL FULLSPKS : STD_LOGIC;
BEGIN
DIVIDECLK: PROCESS (CLK)
VARIABLE COUNT4 :STD_LOGIC_vector(3 downto 0);
BEGIN
PRECLK <= '0'; IF COUNT4>11 THEN PRECLK <= '1'; COUNT4:=\
ELSIF CLK'EVENT AND CLK='1' THEN COUNT4:=COUNT4+1; END IF;
END PROCESS ; GENSPKS:
PROCESS (PRECLK,TONE)
VARIABLE COUNT11 :STD_LOGIC_vector(10 downto 0);
BEGIN
IF PRECLK'EVENT AND PRECLK='1' THEN IF COUNT11=16#7FF# THEN
COUNT11:=TONE;
FULLSPKS <= '1';
ELSE COUNT11:=COUNT11+1;
FULLSPKS <= '0';
END IF;
END IF;
END PROCESS; DELAYSPKS:
PROCESS (FULLSPKS)
VARIABLE COUNT2 : STD_LOGIC;
BEGIN
IF FULLSPKS'EVENT AND FULLSPKS='1' THEN
COUNT2:=NOT COUNT2;
IF COUNT2='1' THEN
SPKS <= '1';
ELSE
SPKS <= '0';
END IF;
END IF;
END PROCESS;
END a;
创建符号：（如图5）
图5
5、MUSIC模块：
Music1:liangzhu_rom(歌曲名：梁祝)
WIDTH=4; DEPTH=256;
ADDRESS_RADIX=DEC;