digitron.v
`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////// // Company: // Engineer: //
// Create Date: 10:33:03 11/14/2010 // Design Name:
// Module Name: digitron // Project Name: // Target Devices: // Tool versions: // Description: //
// Dependencies: //
// Revision:
// Revision 0.01 - File Created // Additional Comments: //
//////////////////////////////////////////////////////////////////////////////////
module digitron(clk,rst_n,sm_cs1,sm_cs2,sm_cs3,sm_cs4,sm_db,ps2_byte); input clk,rst_n;
input [7:0] ps2_byte; output sm_cs1,sm_cs2,sm_cs3,sm_cs4; output [6:0] sm_db;
//计数，2^24=16*10^6;即16*10^6*20ns=0.32s=320ms reg [19:0] cnt;
always @(posedge clk or negedge rst_n)
if(!rst_n) cnt<=25'b0; else cnt<=cnt+1'b1;
reg [3:0] shi,ge;
always @(posedge clk or negedge rst_n) if(!rst_n) begin
shi <= 4'd0; ge <= 4'd0; end
else if(cnt==19'hf_ffff)
begin
shi <= ps2_byte/16; ge <= ps2_byte; end
parameter
seg0 = 7'hc0, seg1 = 7'hf9, seg2 = 7'ha4, seg3 = 7'hb0, seg4 = 7'h99, seg5 = 7'h92, seg6 = 7'h82, seg7 = 7'hf8, seg8 = 7'h80, seg9 =7'h90, sega =7'h88, segb =7'h83, segc =7'hc6, segd =7'ha1, sege =7'h86, segf =7'h8e; //segf =7'hff;
reg [3:0] num; reg [6:0] sm_dbr; always @(num)
case(num)
4'h0:sm_dbr<=seg0;
4'h1:sm_dbr<=seg1;
4'h2:sm_dbr<=seg2;
4'h3:sm_dbr<=seg3;
4'h4:sm_dbr<=seg4;
4'h5:sm_dbr<=seg5;
4'h6:sm_dbr<=seg6;
4'h7:sm_dbr<=seg7;
4'h8:sm_dbr<=seg8;
4'h9:sm_dbr<=seg9;
4'hA:sm_dbr<=sega;
4'hB:sm_dbr<=segb;
4'hC:sm_dbr<=segc;
4'hD:sm_dbr<=segd;
4'hE:sm_dbr<=sege;
4'hF:sm_dbr<=segf;
default:; endcase assign sm_db = sm_dbr;
reg sm_cs2_r,sm_cs1_r; always @(clk or shi or ge) begin
if(cnt[19]) begin
sm_cs2_r = 0; sm_cs1_r = 1; num = shi; end else begin
sm_cs2_r = 1; sm_cs1_r = 0;
num = ge; end end
assign sm_cs4 = 1; assign sm_cs3 = 1;
assign sm_cs2 = sm_cs2_r; assign sm_cs1 = sm_cs1_r; endmodule
Implementation Constrants Flie
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