乐曲硬件演奏电路的EDA设计(8)

2018-12-22 21:58

沈阳工程学院课程设计(论文)

WHEN 104 => ToneIndex <= 9; WHEN 105 => ToneIndex <= 9; WHEN 106 => ToneIndex <= 10; WHEN 107 => ToneIndex <= 9; WHEN 108 => ToneIndex <= 8; WHEN 109 => ToneIndex <= 8; WHEN 110 => ToneIndex <= 6; WHEN 111 => ToneIndex <= 5; WHEN 112 => ToneIndex <= 3; WHEN 113 => ToneIndex <= 3; WHEN 114 => ToneIndex <= 3; WHEN 115 => ToneIndex <= 3; WHEN 116 => ToneIndex <= 8; WHEN 117 => ToneIndex <= 8; WHEN 118 => ToneIndex <= 8; WHEN 119 => ToneIndex <= 8; WHEN 120 => ToneIndex <= 6; WHEN 121 => ToneIndex <= 8; WHEN 122 => ToneIndex <= 6; WHEN 123 => ToneIndex <= 5; WHEN 124 => ToneIndex <= 3; WHEN 125 => ToneIndex <= 5; WHEN 126 => ToneIndex <= 6; WHEN 127 => ToneIndex <= 8;

WHEN 128 => ToneIndex <= 5; WHEN 129 => ToneIndex <= 5; WHEN 130 => ToneIndex <= 5; WHEN 131 => ToneIndex <= 5; when 132 => ToneIndex <= 5; when 133 => ToneIndex <= 5; when 134 => ToneIndex <= 5; when 135 => ToneIndex <= 5; when 136 => ToneIndex <= 0;

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沈阳工程学院课程设计(论文)

when 137 => ToneIndex <= 0; when 138 => ToneIndex <= 0; WHEN OTHERS => NULL; END CASE; END PROCESS; END;

--------------------------------------------------------------------------------------------------------------------- 程序2 数控分频 LIBRARY IEEE;

USE IEEE.STD_LOGIC_1164.ALL; ENTITY Speakera IS

PORT ( clk : IN STD_LOGIC;

Tone : IN INTEGER RANGE 0 TO 16#1FFF#; SpkS : OUT STD_LOGIC ); END;

ARCHITECTURE one OF Speakera IS SIGNAL PreCLK : STD_LOGIC; SIGNAL FullSpkS : STD_LOGIC; BEGIN

DivideCLK : PROCESS(clk)

VARIABLE Count4 : INTEGER RANGE 0 TO 15; BEGIN

PreCLK <= '0';

-- 将CLK进行16分频,PreCLK为CLK的16分频 IF Count4 > 11 THEN PreCLK <= '1'; Count4 := 0;

ELSIF clk'EVENT AND clk = '1' THEN Count4 := Count4 + 1; END IF; END PROCESS;

GenSpkS : PROCESS(PreCLK, Tone)

VARIABLE Count13 : INTEGER RANGE 0 TO 16#1FFF#;

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沈阳工程学院课程设计(论文)

BEGIN

-- 11位可预置计数器

IF PreCLK'EVENT AND PreCLK = '1' THEN IF Count13= 16#1FFF# THEN Count13 := Tone;

FullSpkS <= '1'; ELSE

Count13 := Count13 + 1;

FullSpkS <= '0'; END IF; END IF; END PROCESS;

DelaySpkS : PROCESS(FullSpkS) VARIABLE Count2 : STD_LOGIC; BEGIN

-- 将输出再进行2分频,将脉冲展宽,以使扬声器有足够功率发音 IF FullSpkS'EVENT AND FullSpkS = '1' THEN Count2 := NOT Count2;

IF Count2 = '1' THEN SpkS <= '1';

Else SpkS<='0';END IF;

END IF; END PROCESS; END;

---------------------------------------------------------------------------------------------------------------------- 程序3 音符译码 LIBRARY IEEE;

USE IEEE.STD_LOGIC_1164.ALL; ENTITY ToneTaba IS

PORT ( Index : IN INTEGER RANGE 0 TO 15; CODE : OUT INTEGER RANGE 0 TO 15; HIGH : OUT STD_LOGIC;

Tone : OUT INTEGER RANGE 0 TO 16#7FF# ); END;

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沈阳工程学院课程设计(论文)

ARCHITECTURE one OF ToneTaba IS BEGIN

Search : PROCESS(Index) BEGIN

CASE Index IS -- 译码电路,查表方式,控制音调的预置数 WHEN 0 => Tone <= 2047; CODE <= 0; HIGH <= '0'; WHEN 1 => Tone <= 773; CODE <= 1; HIGH <= '0'; WHEN 2 => Tone <= 912; CODE <= 2; HIGH <= '0'; WHEN 3 => Tone <= 1036; CODE <= 3; HIGH <= '0'; WHEN 5 => Tone <= 1197; CODE <= 5; HIGH <= '0'; WHEN 6 => Tone <= 1290; CODE <= 6; HIGH <= '0'; WHEN 7 => Tone <= 1372; CODE <= 7; HIGH <= '0'; WHEN 8 => Tone <= 1410; CODE <= 1; HIGH <= '1'; WHEN 9 => Tone <= 1480; CODE <= 2; HIGH <= '1'; WHEN 10 => Tone <= 1542; CODE <= 3; HIGH <= '1'; WHEN 12 => Tone <= 1622; CODE <= 5; HIGH <= '1'; WHEN 13 => Tone <= 1668; CODE <= 6; HIGH <= '1'; WHEN 15 => Tone <= 1728; CODE <= 7; HIGH <= '1'; WHEN OTHERS => NULL; END CASE; END PROCESS; END;

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