end if; __end if ____; end process;
qb <= _reg8(0)___; ――输出最低位 end behav; 序列检测答案 library ieee;
use ieee.std_logic_1164.all; entity se is
port(din,clk,clr : in std_logic; ab : out std_logic); end se;
architecture behav of se is
type fsm_st is (s0,s1,s2,s3,s4); signal cstate,nstate : fsm_st; begin
reg:process(clr,clk) begin
if clr='1' then cstate <= s0; --ab <= '0'; elsif clk = '1' and clk'event then cstate <= nstate; end if; end process;
com:process(cstate,din) begin
case cstate is
when s0 => if din = '1' then nstate <= s1; else nstate <= s0; end if; ab <= '0';
when s1 => if din = '1' then nstate <= s2; else nstate <= s0; end if; ab <= '0';
when s2 => if din = '1' then nstate <= s2; else nstate <= s3; end if; ab <= '0';
when s3 => if din = '1' then nstate <= s4; else nstate <= s0; end if; ab <= '0';
when s4 => if din = '1' then nstate <= s1; else nstate <= s0; end if; ab <= '1'; end case; end process; end behav;