data:in std_logic_vector(31 downto 0); anjian1:in std_logic; anjian2:in std_logic; anjian3:in std_logic;
od:out std_logic_vector(15 downto 0); ad:out std_logic_vector(4 downto 0)); end entity;
architecture behav of hw_address is type state is(s0,s1,s2,s3); signal sta:state;
signal addr:std_logic_vector(4 downto 0); begin ad<=addr;
process(anjian1,anjian2,anjian3,clk) begin
if(anjian1='1'and anjian2='1'and anjian3='1')then sta<=s0; od<=x\addr<=\
elsif(clk'event and clk ='1')then case sta is
when s0=>if(anjian1='0')then od<=x\ addr<=\ sta<=s1;
elsif(anjian2='0')then od<=x\ addr<=\ sta<=s1;
elsif(anjian3='0')then od<=x\ addr<=\ sta<=s1; end if; when s1=>addr<=addr;
od<=data(15 downto 0); sta<=s2; when s2=>addr<=addr+'1';
od<=data(31 downto 16); sta<=s3; when s3=>sta<=s3; end case;
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end if; end process; 存储读出程序
library ieee;
use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity hw_adout is port(clk:in std_logic;
inin:in std_logic_vector(15 downto 0); anjian1:in std_logic; anjian2:in std_logic; anjian3:in std_logic;
output:out std_logic_vector(31 downto 0)); end entity;
architecture behav of hw_adout is type state is(s0,s1,s2,s3); signal sta:state;
signal in1:std_logic_vector(15 downto 0); signal out1:std_logic_vector(31 downto 0); begin in1<=inin; output<=out1; process(anjian1,clk) begin
if(anjian1='1'and anjian2='1'and anjian3='1')then sta<=s0;
out1<=x\
elsif(clk'event and clk ='1')then case sta is when s0=>
out1(15 downto 0)<=in1; sta<=s1; when s1=>if(out1=in1)then sta<=s1; else
out1(15 downto 0)<=in1; sta<=s2; end if; when s2=>if(out1=in1)then sta<=s2; else
out1(31 downto 16)<=in1;
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sta<=s3; end if; when s3=>sta<=s3; end case; end if; end process; end behav; 红外发射程序
library ieee;
use ieee.std_logic_1164.all;
entity hw_OUTPUT is
port(CLK:in std_logic;--50MHz kin:in std_logic;
DATA:in std_logic_vector(31 downto 0); IROUT:out std_logic); end entity hw_OUTPUT ;
architecture one of hw_OUTPUT is type state is(s0,s1,s2,s3,s4); signal sta:state;
signal clk_1m:std_logic; --1MHz signal clk_38k:std_logic; --38kHz begin process(CLK)
variable clk_counter:integer range 0 to 25; begin
if(CLK'event and CLK='1')then clk_counter:=clk_counter+1; if(clk_counter=25)then clk_counter:=0; clk_1m<=not clk_1m; end if; end if; end process;
process(CLK)
variable clk_counter:integer range 0 to 658; begin
if(CLK'event and CLK='1')then clk_counter:=clk_counter+1; if(clk_counter=658)then
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clk_counter:=0; clk_38k<=not clk_38k; end if; end if; end process;
process(kin,clk_1m)
variable step:integer range 0 to 32; variable counter:integer range 0 to 100000; begin
if(kin='1')then IROUT<='0'; step:=0; sta<=s1; counter:=0;
elsif(clk_1m'event and clk_1m='1')then case sta is
when s0=>IROUT<='0'; if(counter<100000)then counter:=counter+1; else sta<=s1; counter:=0; end if; when s1=>IROUT<=clk_38k; if(counter<9000)then counter:=counter+1; else sta<=s2; counter:=0; end if; when s2=>IROUT<='0'; if(counter<4500)then counter:=counter+1; else sta<=s3; counter:=0; end if;
when s3=>IROUT<=clk_38k; if(counter<560)then counter:=counter+1; else sta<=s4; counter:=0; end if;
when s4=>IROUT<='0';
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if(DATA(step)='0')then if(counter<565)then counter:=counter+1; elsif(step<32)then sta<=s3; step:=step+1; counter:=0; else sta<=s0; step:=0; counter:=0; end if;
elsif(DATA(step)='1')then
if(counter<1690)then counter:=counter+1; elsif(step<32)then sta<=s3; step:=step+1; counter:=0; else sta<=s0; step:=0; counter:=0; end if; end if; end case; end if; end process;
end architecture one;
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