real[1]='.'; j=2;
for(i=0;i<6;i++) {
real[j++]=sig_dig[i]; } }
else if(pos==-1) {
real[0]='0'; real[1]='.'; real[2]='0'; j=3;
for(i=0;i<6;i++) {
real[j++]=sig_dig[i]; } }
else if(pos==-2) {
real[0]='0'; real[1]='.'; real[2]='0'; real[4]='0'; j=3;
for(i=0;i<6;i++) {
real[j++]=sig_dig[i]; } } }
Verilog HDL部分源代码
/*====================================================== 文件名：spi_interface_out_final.v 功能：SPI通信接口
======================================================*/
module spi_interface_out_final(load,cs,sclk,mosi,miso,lat,
dat0,dat1,dat2,dat3,dat4,dat5,dat6,dat7,
dat8,dat9,dat10,dat11,dat12,dat13,dat14,dat15, dat16,dat17,dat18,dat19,dat20,dat21,dat22,dat23, dat24,dat25,dat26,dat27,dat28,dat29,dat30,dat31 );
input sclk,mosi,cs,load,lat; input [7:0] dat0; input [7:0] dat1; input [7:0] dat2; input [7:0] dat3; input [7:0] dat4; input [7:0] dat5; input [7:0] dat6; input [7:0] dat7; input [7:0] dat8; input [7:0] dat9; input [7:0] dat10; input [7:0] dat11; input [7:0] dat12; input [7:0] dat13; input [7:0] dat14; input [7:0] dat15; input [7:0] dat16; input [7:0] dat17; input [7:0] dat18; input [7:0] dat19; input [7:0] dat20; input [7:0] dat21; input [7:0] dat22; input [7:0] dat23; input [7:0] dat24; input [7:0] dat25; input [7:0] dat26; input [7:0] dat27; input [7:0] dat28; input [7:0] dat29; input [7:0] dat30; input [7:0] dat31; output miso;
reg [15:0] spi_reg; reg [1:0] sel; reg [7:0]
reg0,reg1,reg2,reg3,reg4,reg5,reg6,reg7,reg8,reg9,reg10,reg11,reg12,reg13,reg14,reg15; reg [7:0]
reg16,reg17,reg18,reg19,reg20,reg21,reg22,reg23,reg24,reg25,reg26,reg27,reg28,reg29,reg30,reg31; assign miso=spi_reg[15];
always @ (negedge lat) begin
reg0<=dat0; reg1<=dat1; reg2<=dat2; reg3<=dat3; reg4<=dat4; reg5<=dat5; reg6<=dat6; reg7<=dat7; reg8<=dat8; reg9<=dat9; reg10<=dat10; reg11<=dat11; reg12<=dat12; reg13<=dat13; reg14<=dat14; reg15<=dat15; reg16<=dat16; reg17<=dat17; reg18<=dat18; reg19<=dat19; reg20<=dat20; reg21<=dat21; reg22<=dat22; reg23<=dat23; reg24<=dat24; reg25<=dat25; reg26<=dat26; reg27<=dat27; reg28<=dat28; reg29<=dat29; reg30<=dat30; reg31<=dat31; end
always @ (negedge load or posedge sclk) begin
if(!load) begin
case(spi_reg[4:0])
0:spi_reg[15:8]<=reg0; 1:spi_reg[15:8]<=reg1; 2:spi_reg[15:8]<=reg2; 3:spi_reg[15:8]<=reg3; 4:spi_reg[15:8]<=reg4; 5:spi_reg[15:8]<=reg5; 6:spi_reg[15:8]<=reg6; 7:spi_reg[15:8]<=reg7; 8:spi_reg[15:8]<=reg8; 9:spi_reg[15:8]<=reg9; 10:spi_reg[15:8]<=reg10; 11:spi_reg[15:8]<=reg11; 12:spi_reg[15:8]<=reg12; 13:spi_reg[15:8]<=reg13; 14:spi_reg[15:8]<=reg14; 15:spi_reg[15:8]<=reg15; 16:spi_reg[15:8]<=reg16; 17:spi_reg[15:8]<=reg17; 18:spi_reg[15:8]<=reg18; 19:spi_reg[15:8]<=reg19; 20:spi_reg[15:8]<=reg20; 21:spi_reg[15:8]<=reg21; 22:spi_reg[15:8]<=reg22; 23:spi_reg[15:8]<=reg23; 24:spi_reg[15:8]<=reg24; 25:spi_reg[15:8]<=reg25; 26:spi_reg[15:8]<=reg26; 27:spi_reg[15:8]<=reg27; 28:spi_reg[15:8]<=reg28; 29:spi_reg[15:8]<=reg29; 30:spi_reg[15:8]<=reg30; 31:spi_reg[15:8]<=reg31;
default: spi_reg[15:8]<=reg0; endcase end
else if(cs==0) spi_reg<={spi_reg[14:0],mosi}; else spi_reg<=spi_reg; end
endmodule
/*====================================================== 文件名：control.v
功能：频率计的门控模块
======================================================*/ module control(clk_2hz,en,clr,lat); input clk_2hz;
output clr,en,lat;
reg [3:0] CS,NS; reg en,clr,lat;
parameter state1=4'b0001; parameter state2=4'b0010; parameter state3=4'b0100; parameter state4=4'b1000;
always @ (posedge clk_2hz) begin CS<=NS; end
always @ (CS) begin case(CS)
state1:NS=state2; state2:NS=state3; state3:NS=state4; state4:NS=state1; default:NS=state1; endcase end
always @ (CS) begin case(CS)
state1:{clr,en,lat}=3'b001; state2:{clr,en,lat}=3'b111; state3:{clr,en,lat}=3'b110; state4:{clr,en,lat}=3'b101; default:{clr,en,lat}=3'b001; endcase end