说明：双 4选 1 数据选择器，其地址信号共用，且各有一个低电平的使能端。 LIBRARY ieee;
USE ieee.std_logic_1164.ALL; ENTITY shuangmux41 IS
PORT(a: IN std_logic_vector(3 DOWNTO 0); b: IN std_logic_vector(3 DOWNTO 0); sel : IN std_logic_vector(1 DOWNTO 0); en1,en2 : IN std_logic; y1: OUT std_logic); END shuangmux41;
ARCHITECTURE art OF shuangmux41 IS BEGIN
PROCESS(sel,en1,en2) BEGIN
IF en1='0'AND en2='1' THEN CASE sel IS
WHEN \ WHEN \ WHEN \ WHEN \ WHEN OTHERS=>NULL; END CASE;
( if ) en1='1' AND en2='0' THEN CASE ( SEL ) IS WHEN \ WHEN \ WHEN \ WHEN \ WHEN OTHERS=>NULL; END CASE;
ELSE y1<= (?Z? ) ; END IF; END PROCESS; END;
28. 在下面横线上填上合适的语句，完成具有三态输出的 8d 锁存器的设计。
说明：clr是复位控制输入端，当clr=0时，8位数据输出q[7..0]=0000000。ena是使能控制输入端， 当ena=1时，锁存器处于工作状态，输出q[7..0]=d[7..0]；ena=0时，锁存器的状态保持不变。oe 是三态输入控制端，当oe=1时，输出为高阻态；oe=0时，锁存器为正常输出状态。 LIBRARY ieee;
USE ieee.std_logic_1164.ALL; USE ieee.std_logic_arith.ALL; USE ieee.std_logic_unsigned.ALL; ENTITY latch8 IS
PORT(d: IN std_logic_vector(7 DOWNTO 0); ena,oe,clk,clr: IN std_logic;
q: BUFFER std_logic_vector(7 DOWNTO 0));
END;
ARCHITECTURE aaa OF latch8 IS
SIGNAL q_temp: std_logic_vector(7 DOWNTO 0); BEGIN
PROCESS(clk,oe) BEGIN
IF clr='0' THEN q_temp<=\ ELSIF clk='1' AND ( clk?event ) THEN IF ena='1' THEN q_temp<= ( d ); END IF; END IF;
IF oe=( ?1? ) THEN q<= ( “ZZZZZZZZ” ) ; ELSE q<= q_temp; END IF;
END PROCESS; END aaa;
设计题（28题）
1、完成 2 选 1多路选择器的设计。 library ieee;
use ieee.std_logic_1164.all; entity mux21 is
generic(delay: time); port(a,b,s: in std_logic; y: out std_logic); end;
architecture bh of mux21 is signal q_tmp: std_logic; begin
process(a,b,s) is
variable tmp0,tmp1: std_logic; begin
tmp0:=a and (not s); tmp1:=b and s;
q_tmp<=tmp0 or tmp1; y<=q_tmp after delay; end process; end;
2、完成BCD码转LED共阴译码显示器设计。 library ieee;
use ieee.std_logic_1164.all; ENTITY DECODER IS
PORT(INPUT：RANGE 0 TO 9；DRIVE：OUT BIT_VECTOR(0 TO 6))； END DECODER；
ARCHITECTURE ART OF DECODER IS
BEGIN
WITH INPUT SELECT
DRIVE<=B“1111110” WHEN 0, B“0110000” WHEN 1， B“1101101” WHEN 2， B“1111001” WHEN 3， B“0110011” WHEN 4， B“1011011” WHEN 5， B“1011111” WHEN 6， B“1110000” WHEN 7， B“1111111” WHEN 8， B“1111011” WHEN 9，
B“0000000” WHEN OTHERS； END ARCHITECTURE ART； 3、完成8位移位寄存器的设计。 library ieee;
use ieee.std_logic_1164.all; entity shift is
port(clk,c0: in std_logic;
md: in std_logic_vector(2 downto 0); d: in std_logic_vector(7 downto 0); qb: out std_logic_vector(7 downto 0); cn: out std_logic); end;
architecture bh of shift is
signal reg: std_logic_vector(7 downto 0); signal cy: std_logic; begin
process(clk,md,c0) is begin
if clk'event and clk='1' then case md is
when \
reg(7 downto 1)<=reg(6 downto 0); when \
reg(7 downto 1)<=reg(6 downto 0); when \ eg(6 downto 0)<=reg(7 downto 1); when \
reg(6 downto 0)<=reg(7 downto 1); when \ when others=> reg<=reg;cy<=cy; end case; end if; end process;
cy<=reg(7); cy<=reg(0); qb(7 downto 0)<=reg(7 downto 0); cn<=cy; end;
4、采用CASE语句描述一个四选一数据选择器,当选择端SEL分别为 00,01,10,11时，输出Y 分别输出A,B,C,D。 LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL ENTITY MUX41 IS
PORT(A,B,C,D:IN STD_LOGIC;
SEL:IN STD_LOGIC_VECTOR(1 DOWNTO 0); Y:OUT STD_LOGIC); END MUX41;
ARCHITECTURE BEHAV OF MUX41 IS BEGIN PROCESS(A,B,C,D,SEL) BEGIN
CASE SEL IS
WHEN ”00”=>Y<=A; WHEN ”01”=>Y<=B; WHEN ”10”=>Y<=C; WHEN ”11”=>Y<=D;
WHEN OTHERS=>Y<=0; END CASE； END PROCESS; END BEHAV；
5.设计一位比较器，当A>B时输出Q=1; 否则输出Q=0. LIBRARY IEEE；
USE IEEE.STD_LOGIC_1164.ALL； ENTITY COMP IS
PORT（A，B：IN STD_LOGIC； Q：OUT STD_LOGIC）； END COMP；
ARCHITECTURE BEHAV OF COMP IS BEGIN
PROCESS（A，B） BEGIN
IF A>B THEN Q<=?1?； ELSE Q<=?0?；; END IF； END PROCESS； END BEHAV；
6、写出具有异步清零功能、时钟上升沿触发的D触发器的VHDL描述。 LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL； ENTITY DFF IS
PORT(D, CLK，RESET:IN STD_LOGIC; Q:OUT STD_LOGIC); END DFF;
ARCHITECTURE BEHAV OF DFF IS BEGIN
PROCESS(D,CLK,RESET) BEGIN
IF RESET=?1? THEN Q<=?0?;
ELSIF CLK?EVENT AND CLK=?1?THEN Q<=?D?; END IF; END PROCESS; END BEHAV；
7、写出具有异步清零功能、时钟下降沿触发的D触发器的VHDL描述。 LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL； ENTITY DFF IS
PORT(D, CLK，RESET:IN STD_LOGIC; Q:OUT STD_LOGIC); END DFF;
ARCHITECTURE BEHAV OF DFF IS BEGIN
PROCESS(D,CLK,RESET) BEGIN
IF RESET=?1? THEN Q<=?0?;
ELSIF CLK?EVENT AND CLK=?0?THEN Q<=?D?; END IF; END PROCESS; END BEHAV；
8、完成基本RS触发器的设计。（RS端子低电平有效） LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL； ENTITY DFF IS
PORT(R,S,CLK:IN STD_LOGIC; Q:OUT STD_LOGIC); END DFF;
ARCHITECTURE BEHAV OF DFF IS BEGIN
PROCESS(R,S,CLK) BEGIN
IF CLK?EVENT AND CLK=?1?THEN IF((R=?0?)AND (S=?1?)) THEN Q<=?0?;
ELSIF ((R=?0?)AND (S=?1?)) THEN Q<=?1?; End if; END IF;