ELSIF CLK'EVENT AND CLK = '1' THEN
CASE C_ST IS
-- 15
-- 16
WHEN ST0 => IF DATAIN = \
ELSE C_ST <= ST0; END IF;
-- 17
-- 18 -- 19
Q <= \
WHEN ST1 => IF DATAIN = \
ELSE C_ST <= ST1; END IF;
-- 20
-- 21 -- 22
Q <= \
WHEN ST2 => IF DATAIN = \
ELSE C_ST <= ST0; END IF;
-- 23
-- 24 -- 25
Q <= \
WHEN ST3 => IF DATAIN = \
ELSE C_ST <= ST2; END IF;
-- 26
-- 27 -- 28
Q <= \
WHEN ST4 => IF DATAIN = \
ELSE C_ST <= ST3; END IF;
-- 29
-- 30 -- 31 -- 32
-- 33
Q <= \
END CASE;
END IF;
END PROCESS; END BEHAV;
-- 34 -- 35
1．在程序中存在两处错误，试指出，并说明理由： 在Quartus II中编译时，其中一个提示的错误为： Error (Line 9): VHDL syntax error at MOORE1.vhd(9) near text \ expecting \ 第9行，状态机数据类型声明错误，关键字应为TYPE 第32行，case语句缺少when others处理异常状态情况
2．修改相应行的程序（如果是缺少语句请指出大致的行数）： 错误1 行号： 9 程序改为：SIGNAL 改为 TYPE
错误2 行号： 32 程序改为：之前添加一句 when others => c_st <= st0;
五、阅读下列VHDL程序，说出总体实现了什么功能，并对代码进行解释。(10分)
1. ENTITY mux21a IS
PORT ( a, b, s: IN BIT; y : OUT BIT ); END ENTITY mux21a;
ARCHITECTURE one OF mux21a IS BEGIN
PROCESS (a,b,s) BEGIN
IF s = '0' THEN y <= a ; ELSE y <= b ; END IF;
END PROCESS;
END ARCHITECTURE one
2.LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL; ENTITY TRIS IS
PORT ( CONTROL : IN STD_LOGIC; INN : IN STD_LOGIC; Q : INOUT STD_LOGIC; Y : OUT STD_LOGIC ); END TRIS;
ARCHITECTURE ONE OF TRIS IS BEGIN
PROCESS (CONTROL, INN, Q) BEGIN
IF (CONTROL = '0') THEN Y <= Q; Q <= 'Z'; ELSE
Q <= INN; Y <= 'Z'; END IF; END PROCESS; END ONE;
六、写VHDL程序：（10分）
1. 设计10进制加法计数器，要求含异步清0和同步时钟使能。
注意：时钟信号命名为CLK，使能信号为EN，清零信号为RST，计数输出为CQ。
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL; ENTITY CNT10 IS
PORT (CLK,RST,EN : IN STD_LOGIC;
CQ : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); COUT : OUT STD_LOGIC ); END CNT10;
ARCHITECTURE behav OF CNT10 IS BEGIN
PROCESS(CLK, RST, EN)
VARIABLE CQI : STD_LOGIC_VECTOR(3 DOWNTO 0); BEGIN
IF RST = '1' THEN CQI := (OTHERS =>'0') ; --计数器异步复位 ELSIF CLK'EVENT AND CLK='1' THEN --检测时钟上升沿
IF EN = '1' THEN --检测是否允许计数（同步使能）
IF CQI < 9 THEN CQI := CQI + 1; --允许计数, 检测是否小于9 ELSE CQI := (OTHERS =>'0'); --大于9，计数值清零 END IF; END IF; END IF;
IF CQI = 9 THEN COUT <= '1'; --计数大于9，输出进位信号 ELSE COUT <= '0'; END IF;
CQ <= CQI; --将计数值向端口输出 END PROCESS; END behav;
2.试描述一个带进位输入、输出的8位全加器
端口：A、B为加数，CIN为进位输入，S为加和，COUT为进位输出
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL; ENTITY ADDER8 IS PORT (A, B : IN STD_LOGIC_VECTOR (7 DOWNTO 0); CIN : IN STD_LOGIC; COUT : OUT STD_LOGIC; S : OUT STD_LOGIC_VECTOR (7 DOWNTO 0) ); END ADDER8;
ARCHITECTURE ONE OF ADDER8 IS SIGNAL TS : STD_LOGIC_VECTOR (8 DOWNTO 0); BEGIN TS <= (?0? & A) + (?0? & B) + CIN; S <= TS(7 DOWNTO 0); COUT <= TS(8);
END ONE;
七、VHDL程序设计：（20分）
设计一数据选择器MUX,其系统模块图和功能表如下图所示。试采用下面三种方式中的两种来描述该数据选择器MUX的结构体。
(a) 用if语句。 (b) 用case 语句。 (c) 用when else 语句。
Library ieee;
Use ieee.std_logic_1164.all;
Entity mymux is Port ( sel : in std_logic_vector(1 downto 0); -- 选择信号输入 Ain, Bin : in std_logic_vector(1 downto 0); -- 数据输入 Cout : out std_logic_vector(1 downto 0) ); End mymux;
Architecture one of mymux is Begin Process (sel, ain, bin) Begin If sel = “00” then cout <= ain and bin; Elsif sel = “01” then cout <= ain xor bin; Elsif sel = “10” then cout <= not ain; Else cout <= not bin; End if; End process; End one;
Architecture two of mymux is
Begin Process (sel, ain, bin) Begin Case sel is when “00” => cout <= ain and bin; when “01” => cout <= ain xor bin; when “10” => cout <= not ain; when others => cout <= not bin; End case; End process; End two;
Architecture three of mymux is Begin Cout <= ain and bin when sel = “00” else Ain xor bin when sel = “01” else Not ain when sel = “10” else not bin; End three;
设计一个7段数码显示译码器，并逐行进行解释 LIBRARY IEEE ;
USE IEEE.STD_LOGIC_1164.ALL ; ENTITY DECL7S IS
PORT ( A : IN STD_LOGIC_VECTOR(3 DOWNTO 0); LED7S : OUT STD_LOGIC_VECTOR(6 DOWNTO 0) ) ; END ;
ARCHITECTURE one OF DECL7S IS BEGIN
PROCESS( A ) BEGIN CASE A IS
WHEN \ WHEN \ WHEN \ WHEN \ WHEN \ WHEN \ WHEN \ WHEN \ WHEN \ WHEN \ WHEN \ WHEN \ WHEN \ WHEN \ WHEN \ WHEN \ WHEN OTHERS => NULL ; END CASE ; END PROCESS ; END ;