实现功能：八位串行输入串行输出冒泡排序 源文件：
module bubble_sort(clk,rst,Load,Sort,Send,Data_in,Data_out); input clk,rst,Load,Sort,Send; input [7:0]Data_in; output reg[7:0] Data_out; reg[7:0] A[1:8]; reg[3:0]k; reg[3:0]i,j; reg [2:0]state,nstate; parameter S_rst=3'd0; parameter S_init=3'd1; parameter S_idle=3'd2; parameter S_load=3'd3; parameter S_prep=3'd4; parameter S_sort=3'd5; parameter S_wait=3'd6; parameter S_send=3'd7;
always@(posedge clk or posedge rst) begin end //状态切换
always@(state or Load or Sort or Send or i or k) begin
case(state)
S_rst:
begin end
nstate=S_idle; begin end
if(Load==1'b1)
nstate=S_load; nstate=S_prep; else nstate = S_idle; else if(Sort==1'b1)
nstate=S_init;
if(rst) else
state<=nstate; state<=S_rst;
S_init: S_idle:
end
S_load:
begin end
nstate=S_sort; begin end begin end begin end
nstate=S_rst; if(k==4'd8) else
nstate=S_send; nstate=S_init; if(Send==1'b1) else
nstate=S_wait; nstate=Send; if(i<=j) else
nstate=S_wait; nstate=S_sort; nstate=S_sort; nstate=S_send; else if(i<=4'd8) else if(Send==1'b1) if(k==4'd8) else
nstate=S_load; nstate=S_init;
S_prep: S_sort:
S_wait:
S_send:
default:
endcase
//数据传送
always@(posedge clk) begin
case(state)
S_rst: ;
S_init:
begin end begin end begin end begin end begin
if(i<=j)
if(A[j-1]>A[j])
begin
A[j]<=A[j-1]; A[j-1]<=A[j]; j<=j-1'b1;
if(A[j-1]>A[j])
begin end
A[j]<=A[j-1]; A[j-1]<=A[j]; j<=j-1'b1;
if(k<4'd8)
begin end
k<=k+1'b1; A[1]<=Data_in; A[2]<=A[1]; A[3]<=A[2]; A[4]<=A[3]; A[5]<=A[4]; A[6]<=A[5]; A[7]<=A[6]; A[8]<=A[7];
if((Load==1'b0)&&(Sort==1'b1))
begin end
j<=4'd8; i<=4'd2;
k<=4'd0;
S_idle:
S_load:
S_prep:
S_sort:
end
end
else
end j<=j-1'b1;
else if(i<=4'd8)
begin end k<=4'd0;
j<=4'd8; i<=i+1'b1;
else if(Send==1'b1)
S_wait:
if(Send==1'b1)
k<=4'd0;
S_send:
begin end
if(k<4'd8)
begin end
k<=k+1'b1; A[1]<=8'd0; A[2]<=A[1]; A[3]<=A[2]; A[4]<=A[3]; A[5]<=A[4]; A[6]<=A[5]; A[7]<=A[6]; A[8]<=A[7]; Data_out<=A[8];
default: ;
endcase
//end
Endmodule
测试文件：
`timescale 1 ns/ 1 ps module bubble_sort_vlg_tst(); reg [7:0]Data_in; reg Load; reg Send; reg Sort; reg clk; reg rst;
wire [7:0]Data_out; bubble_sort i1 ( ); initial begin Data_in=8'd0; clk=1'b0;
forever #10 clk=~clk; $display(\end initial begin
rst=1'b1;Load=1'b0;Sort=1'b0;Send=1'b0; #100 rst=1'b0;Load=1'b1; #60 Data_in=8'd37; #20 Data_in=8'd29; #20 Data_in=8'd01; #20 Data_in=8'd19; #20 Data_in=8'd89; #20 Data_in=8'd10; #20 Data_in=8'd12; #20 Data_in=8'd182; #20 Load=1'b0; Sort=1'b1; Send=1'b1; #2000 $stop; end endmodule 仿真结果：
.Data_in(Data_in), .Data_out(Data_out), .Load(Load), .Send(Send), .Sort(Sort), .clk(clk), .rst(rst)
输入数据波形
输出数据波形