华科 - HUST - 微机原理 - 类MIPS单周期微处理器设计 - 实验报告(3)

dram dmem(

.a(aluRes[7:2]), .d(RtData), .clk(!clkin), .we(memwrite), .spo(memreaddata) );

irom_number imem( .a(pc[8:2]), .clk(clkin), .spo(inst) );

regFile regfile(

.RsAddr(inst[25:21]), .RtAddr(inst[20:16]), .clk(!clkin), .reset(reset),

.regWriteAddr(mux1), .regWriteData(mux3), .regWriteEn(regwrite), .RsData(RsData), .RtData(RtData) );

signext signext(.inst(inst[15:0]),.data(expand));

assign mux1=reg_dst?inst[15:11]:inst[20:16]; assign mux2=alu_scr?expand:RtData;

assign mux3=memtoreg?memreaddata:aluRes; assign mux4=choose4?address:add4; assign mux5=jmp?jmpaddr:mux4; assign choose4=branch&zero; assign expand2=expand<<2;

assign jmpaddr={add4[31:28],inst[25:0],2'b00}; assign address=pc+expand2; endmodule

四．ROM程序设计

本程序的目的是将自己学号的ASCII码存储到数据存储器中。每个字存储一个ASCII码。汇编程序代码如下：

main:

addi $2,$0,85 #U sw $2,0($3)

addi $2,$0,50 #2 sw $2,4($3)

addi $2,$0,48 #0 sw $2,8($3)

addi $2,$0,49 #1 sw $2,12($3)

addi $2,$0,51 #3 sw $2,16($3)

addi $2,$0,49 #1 sw $2,20($3)

addi $2,$0,51 #3 sw $2,24($3)

addi $2,$0,54 #6 sw $2,28($3)

addi $2,$0,53 #5 sw $2,32($3)

addi $2,$0,49 #1 sw $2,36($3) j main

对应的机器码为：

MEMORY_INITIALIZATION_RADIX=16; MEMORY_INITIALIZATION_VECTOR= 20020055, ac620000, 20020032, ac620004, 20020030, ac620008, 20020031, ac62000c, 20020033, ac620010, 20020031, ac620014, 20020033, ac620018, 20020036, ac62001c, 20020035, ac620020, 20020031, ac620024,

08100000,

特别值得注意的有两点：一是寄存器组中的$1号寄存器被系统占用，在编写汇编代码时不可使用，否则Qtspim会报错；二是机器码的最后一条指令是跳转到程序入口main处，应将机器码改为08100000。

把coe文件导入irom中，如下图所示：

四.模块仿真

1.寄存器组仿真： 代码如下:

module regsim; // Inputs reg clk; reg reset; reg [31:0] regWriteData; reg [4:0] regWriteAddr; reg regWriteEn; reg [4:0] RsAddr; reg [4:0] RtAddr; // Outputs wire [31:0] RsData; wire [31:0] RtData; // Instantiate the Unit Under Test (UUT) regFile uut ( .clk(clk), .reset(reset), .regWriteData(regWriteData), .regWriteAddr(regWriteAddr), .regWriteEn(regWriteEn), .RsData(RsData), .RtData(RtData), .RsAddr(RsAddr), .RtAddr(RtAddr) ); integer i; initial begin // Initialize Inputs clk = 0; reset = 0; regWriteData = 0; regWriteAddr = 0; regWriteEn = 0; RsAddr = 0; RtAddr = 0; // Wait 100 ns for global reset to finish #100; // Add stimulus here regWriteData=32'h55aaaa55; regWriteEn=1;

reset=1; #100; reset=0; end

parameter PERIOD = 20; always begin clk = 1'b0; #(PERIOD/2) clk = 1'b1; #(PERIOD/2); end always begin for(i = 31; i>= 1; i=i-1) begin regWriteAddr = i; RsAddr=i; #PERIOD; end end Endmodule 结果如下:

Reset高电平下输出为0，Reset无效后，正常输入和输出数据，Reset正常工作。