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8.3状态条件寄存器
只保留了用到的SF LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL; ENTITY PSW IS PORT(
S,LDPSW: IN STD_LOGIC; SF: OUT STD_LOGIC ); END PSW;
ARCHITECTURE A OF PSW IS BEGIN
PROCESS(LDPSW) BEGIN
IF(LDPSW'EVENT AND LDPSW='1') THEN SF<=S; END IF; END PROCESS; END A;
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8.4微程序控制器
内部结构：
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( 1 ) 地址转移逻辑电路
程序：
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL; ENTITY ADDR IS PORT(
I4,I3,I2,I1: IN STD_LOGIC; SF,P2,P1,T4: IN STD_LOGIC;
SE6,SE5,SE4,SE3,SE2,SE1: OUT STD_LOGIC );
END ADDR;
ARCHITECTURE A OF ADDR IS BEGIN
SE6 <= '1';
SE5 <= NOT(NOT(SF) AND P2 AND T4); SE4 <= NOT(I4 AND P1 AND T4); SE3 <= NOT(I3 AND P1 AND T4); SE2 <= NOT(I2 AND P1 AND T4); SE1 <= NOT(I1 AND P1 AND T4); END A;
（2）微地址寄存器
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微地址寄存器uar的内部结构：
程序：
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL; ENTITY MMM IS PORT(
SE,T2,D,CLR: IN STD_LOGIC; UA: OUT STD_LOGIC
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);
END MMM;
ARCHITECTURE A OF MMM IS BEGIN
PROCESS(CLR,SE,T2) BEGIN IF(CLR='0') THEN UA <= '0'; ELSIF(SE='0') THEN UA <= '1'; ELSIF(T2'EVENT AND T2='1') THEN UA <= D; END IF; END PROCESS;
（3）微地址转换器F1
程序：
LIBRARY IEEE;
USE IEEE.STD_LOGIC_116 ALL; ENTITY F1 IS PORT(
UA5,UA4,UA3,UA2,UA1,UA0:IN STD_LOGIC; D:OUT STD_LOGIC_VECTOR(5 DOWNTO 0) );
END F1;
ARCHITECTURE A OF F1 IS BEGIN
D(5)<=UA5; D(4)<=UA4; D(3)<=UA3; D(2)<=UA2; D(1)<=UA1; D(0)<=UA0; END A;