IF RST=’1’ THEN ST <=s0；
ELSIF CLK’EVENT AND CLK=’1’ THEN ST <= NST; END IF ;
END PROCESS REG;
SOUT <= ‘1’ WHEN ST=s8 ELSE ‘0’; END behav；
Mealy型序列检测器例7-7课本250页
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL; ENTITY SCHK IS
PORT(DIN,CLK,RST : IN STD_LOGIC; --串行输入
SOUT : OUT STD_LOGIC);
END SCHK;
ARCHITECTURE behav OF SCHK IS
TYPE states IS (s0,s1,s2,s3,s4,s5,s6,s7,s8);
SIGNAL ST: states :=s0; --设定现态变量和次态变量 BEGIN
PROCESS(ST, DIN) BEGIN --组合进程，规定各状态转换方式 IF RST =’1’ THEN ST <= s0; ELSIF CLK’EVENT AND CLK=’1’ THEN CASE ST IS --11010011
WHEN s0=> IF DIN =’1’ THENST<=s1;ELSEST<=s0;END IF; WHEN s1=> IF DIN =’1’ THEN ST<=s2;ELSE ST<=s0;END IF; WHEN s2=> IF DIN =’0’THEN ST<=s3;ELSE ST<=s0;END IF; WHEN s3=> IF DIN =’1’ THEN ST<=s4;ELSE ST<=s0;END IF; WHEN s4=> IF DIN =’0’ THEN ST<=s5;ELSE ST<=s0;END IF; WHEN s5=> IF DIN =’0’ THEN ST<=s6;ELSE ST<=s0;END IF; WHEN s6=> IF DIN =’1’ THEN ST<=s7;ELSEST<=s0;END IF; WHEN s7=> IF DIN =’1’ THEN ST<=s8;ELSE ST<=s0;END IF; WHEN s8=> IF DIN =’0’ THEN ST<=s3;ELSE ST<=s0;END IF; WHEN OTHERS =>ST<=s0; END CASE ;
IF (ST=s8) THEN SOUT <=’1’ ; ELSE SOUT <=’0’ ; END IF; END IF ; END PROCESS; END behav；
3-6数控分频器的设计（实验书）
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL; ENTITY LI36 IS
PORT (CLK:IN STD_LOGIC;
D:IN STD_LOGIC_VECTOR(7 DOWNTO 0); FOUT:OUT STD_LOGIC); END;
ARCHITECTURE one OF LI36 IS
SIGNAL FULL:STD_LOGIC; BEGIN
P_REG:PROCESS(CLK)
VARIABLE CNT8:STD_LOGIC_VECTOR(7 DOWNTO 0); BEGIN
IF CLK'EVENT AND CLK='1' THEN IF CNT8=\ CNT8:=D; FULL<='1';
ELSE CNT8:=CNT8+1; FULL<='0'; END IF; END IF;
END PROCESS P_REG; P_DIV:PROCESS(FULL)
VARIABLE CNT2:STD_LOGIC; BEGIN
IF FULL'EVENT AND FULL='1' THEN CNT2 :=NOT CNT2;
IF CNT2='1' THEN FOUT <='1' ;ELSE FOUT<='0'; END IF; END IF;
END PROCESS P_DIV; END;
例3-3设计含异步清零和同步时钟使能的加法计数器（实验书）
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL; ENTITY Vhdl1 IS
PORT (CLK,RST,EN : IN STD_LOGIC;
CQ: OUT STD_LOGIC_VECTOR(3 DOWNTO 0); COUT: OUT STD_LOGIC ); END Vhdl1;
ARCHITECTURE behav OF Vhdl1 IS BEGIN
PRCCESS(CLK,RST,EN)
VARIABLE CQI: STD_LOGIC_VECTOR(3 DOWNTO 0); BEGIN
IF RST = '1' THEN CQI := (OTHERS =>'0'); ELSIF CLK'EVENT AND CLK='1' THEN IF EN='1' THEN
IF CQI<9 THEN CQI := CQI+1; ELSE CQI := (OTHERS =>'0'); END IF;
END IF; END IF;
IF CQI=9 THEN COUT <= '1'; ELSE COUT <= '0'; END IF; CQ <= CQI; END PROCESS; END behav;
例3-4七段数码显示译码器设计（实验书）
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL; ENTITY Vhdl1 IS
PORT ( A : IN STD_LOGIC_VECTOR(3 DOWNTO 0); LED7S: OUT STD_LOGIC_VECTOR(6 DOWNTO 0)); END ;
ARCHITECTURE one OF Vhdl1 IS BEGIN
PRCCESS(A) BEGIN CASE A IS
WHEN \ <=\ WHEN \ <=\ WHEN \ <=\ WHEN \ <=\ WHEN \ <=\ WHEN \ <=\ WHEN \ <=\ WHEN \ <=\ WHEN \ <=\ WHEN \ <=\ WHEN \ <=\ WHEN \ <=\ WHEN \ <=\ WHEN \ <=\ WHEN \ <=\ WHEN \ <=\ WHEN OTHERS => NULL; END CASE ; END PROCESS; END ;
四选一选择器：【例5-7】（课本上的例子） LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY mux4 IS
PORT (i0, i1, i2, i3, a, b : IN STD_LOGIC; q : OUT STD_LOGIC); END mux4;
ARCHITECTURE body_mux4 OF mux4 IS BEGIN
process(i0,i1,i2,i3,a,b)
variable muxval : integer range 7 downto 0; begin
muxval := 0;
if (a = '1') then muxval := muxval + 1; end if; if (b = '1') then muxval := muxval + 2; end if; case muxval is
when 0 => q <= i0; when 1 => q <= i1; when 2 => q <= i2; when 3 => q <= i3; when others => null; end case;
end process; END body_mux4;
半减器（两种方式）：（双向分频器没找到，减法器没找到）