EDA课程设计乒乓球游戏机vhd语言l - 图文(2)

2019-03-04 14:14

i<=0;count1<=0;count2<=0;count5<=0;count6<=0; elsif clk_1'event and clk_1='1' then --当处于时钟inclock上升沿时 if count1=10 then count1<=0;count5<=1;

elsif count1=1 and count5=1 then

i<=0;count1<=0;count5<=0;count3<=count3+1;count2<=0;count6<=0; elsif count2=10 then count2<=0;count6<=1;

elsif count2=1 and count6=1 then i<=0;count1<=0;count2<=0;count4<=count4+1;count5<=0;count6<=0; elsif count3=4 or count4=4 then

i<=9;music_begin<=1;startbutton=’0’; elsif startbutton='0' then i<=0;count1<=0;count2<=0;count3<=0;count4<=0;count5<=0;count6<=0; else --以下case语句是程序中最关键的状态机部分 case state is when waitserve=>

--进程处于等待发球状态

case serve is when \ when \ when \ when “00”=> i<=0;sound<=”0”; end case; when light1on=> --进程处于第一盏灯亮状态 i<=2; if hit2='1' or hit22=’1’ then i<=0; count1<=count1+1;sound<=”1”state<=waitserve; else state<=ballmoveto2; end if; when light8on=> --进程处于第八盏灯亮状态 i<=7; if hit1='1' or hit11=”1” then i<=0; count2<=count2+1;sound<=”1”;state<=waitserve; else state<=ballmoveto1; end if; when ballmoveto1=> --进程处于球向甲移动状态 if hit1='1' then i<=0; count2<=count2+1;sound<=”1”;state<=waitserve;

elsif i=2 then i<=1; state<=allow1hit; else i<=i-1; end if; when ballmoveto2=> --进程处于球向乙移动状态 if hit2='1'then i<=0; count1<=count1+1; sound<=”1”;state<=waitserve; elsif i=7 then i<=8; state<=allow2hit; else i<=i+1; end if; when allow1hit=> --进程处于允许甲击球状态 if hit1='1' then i<=2; state<=ballmoveto2; else count2<=count2+1;i<=0;sound<=”1”; state<=waitserve; end if;

if hit11='1' then i<=2; state<=ballmoveto2; else count2<=count2+1;i<=0;sound<=”1”; state<=waitserve; end if; when allow2hit=> --进程处于允许乙击球状态 if hit2='1'then i<=7;state<=ballmoveto1; else count1<=count1+1;i<=0;sound<=”1”; state<=waitserve; end if;

if hit22='1'then i<=7;state<=ballmoveto1; else count1<=count1+1;i<=0;sound<=”1”; state<=waitserve; end if; end case; end if; end if; end process;

counta<=count1;countb<=count2;countc<=count3;countd<=count4;counte<=count5;countf<=count6;

process(clk_1)

if (clk_1'event and clk_1='1')then--进程处i信号控制发光二极管的亮暗 light<=\

\\\\\\\\

End process; --其他情况所有发光二极管都暗 end one; 分频模块 library IEEE;

use IEEE.std_logic_1164.all; use ieee.std_logic_arith.all;

use IEEE.std_logic_unsigned.all; entity division16 is port( cp:in std_logic; clk_4:out std_logic ); end division16;

architecture division_body of division16 is signal count:std_logic_vector(3 downto 0); begin

process(cp) begin

if(cp'event and cp='1')then if(count=\count<=(others=>'0'); else

count<=count+1; end if; end if;

end process; process(cp) begin

if(cp'event and cp='1')then if(count=\clk_4<='1'; else

clk_4<='0'; end if; end if;

end process;

end division_body; 译码器部分

library ieee;

use ieee.std_logic_1164.all; entity disp is

port(d:in std_logic_vector(3 downto 0); q:out std_logic_vector(6 downto 0)); end disp;

architecture disp_arc of disp is begin process(d) begin case d is

when \ when \ when \ when \ when \ when \ when \ when \ when \ when \ when others=>q<=\ end case; end process; end disp_arc; 数码管选择 LIBRARY IEEE;

USE IEEE.STD_LOGIC_1164.ALL; ENTITY mux2 IS

PORT(a,b: IN STD_LOGIC_VECTOR(6 downto 0); sel: IN STD_LOGIC;

c:OUT STD_LOGIC_VECTOR(6 downto 0)); END mux2;

ARCHITECTURE example OF mux2 IS BEGIN

PROCESS(sel) BEGIN IF(SEL='1')THEN c<=a; ELSE c<=b; END IF;

END PROCESS; END example;

音乐模块(两只老虎) library IEEE;

use IEEE.std_logic_1164.all; use IEEE.std_logic_unsigned.all; entity music is

port ( music_begin:in std_logic; clk_4:in std_logic; clk:in std_logic; music_out:out std_logic ); end music;

architecture music_body of music is constant m1:integer:=637;--955; constant m2:integer:=587;--851; constant m3:integer:=505;--758; constant m4:integer:=468;--716; constant m5:integer:=425;--639; constant m6:integer:=379;--569; constant m7:integer:=330;--506; constant m0:integer:=0;

signal counter:integer range 0 to 67; signal count:integer range 0 to 1000; signal sub:integer range 0 to 1000; signal carrier:std_logic;

signal pat,pat1,pat2:std_logic; begin

process(clk) begin if(clk'event and clk='1')then if(carrier='1') then sub<=count; else sub<=sub-1; end if; end if; end process; process(sub) begin if(sub=0) then pat<='1'; else pat<='0'; end if; carrier<=pat; end process;


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