/* MICM 0 microphone mute: disabled */ \\ /* MICB 1 microphone boost: enabled */ \\ \\ 0x0000, /* Set-Up Reg 5 Digital audio path control */ \\
/* XXXXX 00000 reserved */ \\ /* DACM 0 DAC soft mute: disabled */ \\ /* DEEMP 00 deemphasis control: disabled */ \\ /* ADCHP 0 ADC high-pass filter: disabled */ \\
\\ 0x0000, /* Set-Up Reg 6 Power down control */ \\ /* X 0 reserved */ \\ /* OFF 0 device power: on (i.e. not off) */ \\
/* CLK 0 clock: on */ \\ /* OSC 0 oscillator: on */ \\ /* OUT 0 outputs: on */ \\ /* DAC 0 DAC: on */ \\ /* ADC 0 ADC: on */ \\ /* MIC 0 microphone: on */ \\ /* LINE 0 line input: on */ \\ \\ 0x0043, /* Set-Up Reg 7 Digital audio interface format */ \\
/* XX 00 reserved */ \\ /* MS 1 master/slave mode: master */ \\ /* LRSWAP 0 DAC left/right swap: disabled */ \\ /* LRP 0 DAC lrp: MSB on 1st BCLK */ \\ /* IWL 00 input bit length: 16 bit */ \\ /* FOR 11 data format: DSP format */ \\ \\ 0x0019, /* Set-Up Reg 8 Sample rate control */ \\
/* X 0 reserved */ \\ /* CLKOUT 1 clock output divider: 2 (MCLK/2) */ \\ /* CLKIN 0 clock input divider: 2 (MCLK/2) */ \\ /* SR, BOSR 00000 sampling rate: ADC 48 kHz DAC 48 kHz */ \\ /* USB/N 1 clock mode select (USB/normal): USB */ \\ \\ 0x0001 /* Set-Up Reg 9 Digital interface activation */ \\
/* XX..X 00000000 reserved */ \\ /* ACT 1 active */ \\ }
/* ------------------------------------------------------------------------ *
* Control Registers for: DSP MCBSP1 ( DSP_MCBSP1_ ) * * ------------------------------------------------------------------------ */
#define DSP_MCBSP1_DRR2 *( VUint16* )0xE1011800 #define DSP_MCBSP1_DRR1 *( VUint16* )0xE1011802
#define DSP_MCBSP1_DXR2 *( VUint16* )0xE1011804 #define DSP_MCBSP1_DXR1 *( VUint16* )0xE1011806 #define DSP_MCBSP1_SPCR2 *( VUint16* )0xE1011808 #define DSP_MCBSP1_SPCR1 *( VUint16* )0xE101180A #define DSP_MCBSP1_RCR2 *( VUint16* )0xE101180C #define DSP_MCBSP1_RCR1 *( VUint16* )0xE101180E #define DSP_MCBSP1_XCR2 *( VUint16* )0xE1011810 #define DSP_MCBSP1_XCR1 *( VUint16* )0xE1011812 #define DSP_MCBSP1_SRGR2 *( VUint16* )0xE1011814 #define DSP_MCBSP1_SRGR1 *( VUint16* )0xE1011816 #define DSP_MCBSP1_MCR2 *( VUint16* )0xE1011818 #define DSP_MCBSP1_MCR1 *( VUint16* )0xE101181A #define DSP_MCBSP1_RCERA *( VUint16* )0xE101181C #define DSP_MCBSP1_RCERB *( VUint16* )0xE101181E #define DSP_MCBSP1_XCERA *( VUint16* )0xE1011820 #define DSP_MCBSP1_XCERB *( VUint16* )0xE1011822 #define DSP_MCBSP1_PCR0 *( VUint16* )0xE1011824 #define DSP_MCBSP1_RCERC *( VUint16* )0xE1011826 #define DSP_MCBSP1_RCERD *( VUint16* )0xE1011828 #define DSP_MCBSP1_XCERC *( VUint16* )0xE101182A #define DSP_MCBSP1_XCERD *( VUint16* )0xE101182C #define DSP_MCBSP1_RCERE *( VUint16* )0xE101182E #define DSP_MCBSP1_RCERF *( VUint16* )0xE1011830 #define DSP_MCBSP1_XCERE *( VUint16* )0xE1011832 #define DSP_MCBSP1_XCERF *( VUint16* )0xE1011834 #define DSP_MCBSP1_RCERG *( VUint16* )0xE1011836 #define DSP_MCBSP1_RCERH *( VUint16* )0xE1011838 #define DSP_MCBSP1_XCERG *( VUint16* )0xE101183A #define DSP_MCBSP1_XCERH *( VUint16* )0xE101183C
/* ------------------------------------------------------------------------ *
* Control Registers for: Inter-Integrated Circuit ( I2C_ ) * ------------------------------------------------------------------------ */ #define I2C_REV *( VUint16* )0xFFFB3800 #define I2C_IE *( VUint16* )0xFFFB3804 #define I2C_STAT *( VUint16* )0xFFFB3808 #define I2C_SYSS *( VUint16* )0xFFFB3810 #define I2C_BUF *( VUint16* )0xFFFB3814 #define I2C_CNT *( VUint16* )0xFFFB3818 #define I2C_DATA *( VUint16* )0xFFFB381C #define I2C_SYSC *( VUint16* )0xFFFB3820 #define I2C_CON *( VUint16* )0xFFFB3824 #define I2C_OA *( VUint16* )0xFFFB3828 #define I2C_SA *( VUint16* )0xFFFB382C
* #define I2C_PSC *( VUint16* )0xFFFB3830 #define I2C_SCLL *( VUint16* )0xFFFB3834 #define I2C_SCLH *( VUint16* )0xFFFB3838 #define I2C_SYSTEST *( VUint16* )0xFFFB383C
/* ------------------------------------------------------------------------ *
* Register Parameters for I2C_STAT ( I2C_STAT_ ) * * ------------------------------------------------------------------------ */
#define I2C_STAT_SBD 0x8000 // Single byte data #define I2C_STAT_BB 0x1000 // Bus busy
#define I2C_STAT_ROVR 0x0800 // Receive overrun #define I2C_STAT_XUDF 0x0400 // Transmit underflow #define I2C_STAT_AAS 0x0200 // Address as slave #define I2C_STAT_GC 0x0020 // General call
#define I2C_STAT_XRDY 0x0010 // Transmit data ready #define I2C_STAT_RRDY 0x0008 // Receive data ready #define I2C_STAT_ARDY 0x0004 // Register access ready #define I2C_STAT_NACK 0x0002 // No acknowledgment #define I2C_STAT_AL 0x0001 // Arbitration lost
/* ------------------------------------------------------------------------ *
* Register Parameters for I2C_CON ( I2C_CON_ ) * * ------------------------------------------------------------------------ */
#define I2C_CON_I2C_EN 0x8000 // I2C module enable #define I2C_CON_BE 0x4000 // Big endian mode #define I2C_CON_STB 0x0800 // Start byte mode #define I2C_CON_MST 0x0400 // Master/slave mode #define I2C_CON_TRX 0x0200 // TX/RX mode #define I2C_CON_TX 0x0200 // TX mode #define I2C_CON_RX 0x0000 // RX mode
#define I2C_CON_XA 0x0100 // Expand address #define I2C_CON_STP 0x0002 // Stop condition #define I2C_CON_STT 0x0001 // Start condition /* ------------------------------------------------------------------------ *
* I2C Transfer modes * * ------------------------------------------------------------------------ */
#define OSK5912_I2C_MODE_SADP 3 // (S)tart..(A)ddr..(D)ata..(n)..sto(P) #define OSK5912_I2C_MODE_SADD 2 // (S)tart..(A)ddr..(D)ata..(n)..(D)ata /* Internal codec state used to simulate read/write functionality */
static OSK5912_AIC23_Config codecstate = OSK5912_AIC23_DEFAULTCONFIG;
/* Open the codec with id and return handle */ OSK5912_AIC23_CodecHandle OSK5912_AIC23_openCodec( Uint32 OSK5912_AIC23_Config *Config);
id,
/* Set codec register regnum to value regval */
void OSK5912_AIC23_rset(OSK5912_AIC23_CodecHandle hCodec, Uint16 regnum,
Uint16 regval);
/* Configure the codec register values */
void OSK5912_AIC23_config(OSK5912_AIC23_CodecHandle hCodec,
OSK5912_AIC23_Config *Config);
/* Write to an I2C slave device */
Uint16 OSK5912_I2C_write( Uint16 slave_addr, Uint8* data, Uint16 length ); /*
* ======== OSK5912_AIC23_rset ======== * Set codec register regnum to value regval */
void OSK5912_AIC23_rset( OSK5912_AIC23_CodecHandle hCodec, Uint16 regnum, Uint16 regval ) {
Uint16 buf = ( ( regval & 0x00FF ) << 8 ) | ( regnum << 1 ) | ( regval >> 8 ); OSK5912_I2C_write( OSK5912_AIC23_I2CADDR, ( Uint8* )&buf, 2 ); codecstate.regs[regnum] = regval; }
* ======== OSK5912_AIC23_config ======== * Set the default codec register config values
void OSK5912_AIC23_config( OSK5912_AIC23_CodecHandle hCodec, OSK5912_AIC23_Config *Config ) {
int i;
/* Use default parameters if none are given */ if ( Config == NULL ) Config = &codecstate;
/* Configure power down register first */
OSK5912_AIC23_rset( hCodec, OSK5912_AIC23_POWERDOWN, Config -> regs[OSK5912_AIC23_POWERDOWN] );
/* Assign each register */
for ( i = 0; i < OSK5912_AIC23_NUMREGS; i++ ) if ( i != OSK5912_AIC23_POWERDOWN )
OSK5912_AIC23_rset( hCodec, i, Config -> regs[i] ); }
/*
* ======== OSK5912_AIC23_openCodec ======== * Open the codec and return a codec handle */
OSK5912_AIC23_CodecHandle OSK5912_AIC23_openCodec( Uint32 id,
OSK5912_AIC23_Config *Config ) {
/* Reset the AIC23 */
OSK5912_AIC23_rset( 0, OSK5912_AIC23_RESET, 0 );
/* Configure the rest of the AIC23 registers */ OSK5912_AIC23_config( 0, Config );
/* Config MCBSP */
DSP_MCBSP1_PCR0 = 0x0003; DSP_MCBSP1_RCR1 = 0x0140; DSP_MCBSP1_RCR2 = 0x0000; DSP_MCBSP1_XCR1 = 0x0140; DSP_MCBSP1_XCR2 = 0x0000; DSP_MCBSP1_SRGR1 = 0x0000; DSP_MCBSP1_SRGR2 = 0x0000; DSP_MCBSP1_SPCR1 = 0x0001; DSP_MCBSP1_SPCR2 = 0x0101;
/* Return 0 as a handle */ return 0; }
/* ------------------------------------------------------------------------ *
* OSK5912_I2C_write( Uint16 slave_addr, Uint8* data, Uint16 length ) * Write to I2C * ------------------------------------------------------------------------ */
/* ------------------------------------------------------------------------ *
* OSK5912_I2C_write( slave_addr, data, length ) * Write to I2C * Returns: * 0 - Pass * 1001 - Fail ( Errors - Arbitration Lost ) * 1002 - Fail ( Errors - NACK ) * 2001 - Fail ( Timeout - Bus Busy ) * 2002 - Fail ( Timeout - Write ) * ------------------------------------------------------------------------ */
*
* *
* * * *
* * *