现代电子系统设计课程设计说明书
附录1 ROM
addr 0 +000 内容及参考程序：
+001 +010 +011 0001001000000000000 0010000100000000001 0011001100000000010 0100010100000000011 +100 +101 +110 +111 0001001000000000100 0010000100000000101 0011001100000000110 0100010100000000111 一 decd程序 library ieee ;
use ieee.std_logic_1164.all ; use ieee.std_logic_unsigned.all; entity decd is
port ( clk2,ud,en: in std_logic ;
dw : out std_logic_vector( 1 downto 0 ) ; sp : out std_logic_vector (3 downto 0 )) ; end ;
architecture one of decd is
signal xh : std_logic_vector ( 1 downto 0 ) ; begin
process( xh ) begin
case xh is
when \ when \ when \ when \ when others => null ; end case ; end process ;
process (clk2 ) begin
if en='1' then
if clk2'event and clk2 = '1' then
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现代电子系统设计课程设计说明书
if ud='1' then
if xh =\ else
xh <= xh +'1' ; end if ; else
if xh =\ else
xh <= xh -'1' ; end if ; end if; end if; end if; end process ; dw <= xh ; end ;
二 CNT5程序 LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL; ENTITY CNT5 IS PORT(
CLK:IN STD_LOGIC;
AA:OUT STD_LOGIC_VECTOR(3 DOWNTO 0) ); END CNT5;
ARCHITECTURE FRE OF CNT5 IS
SIGNAL CNT:STD_LOGIC_VECTOR(3 DOWNTO 0); BEGIN
PROCESS(CLK) BEGIN
IF CLK'EVENT AND CLK ='1' THEN CNT<=CNT+1; END IF; END PROCESS;
AA<=CNT(3 DOWNTO 0); END;
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现代电子系统设计课程设计说明书
三 CMP程序 LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL; ENTITY CMP IS PORT(
A:IN STD_LOGIC_VECTOR(3 DOWNTO 0); B:IN STD_LOGIC_VECTOR(3 DOWNTO 0); AGB:OUT STD_LOGIC ); END CMP;
ARCHITECTURE C OF CMP IS BEGIN
PROCESS(A,B) BEGIN
IF B<=A THEN AGB<='1'; ELSIF B>A THEN AGB<='0'; END IF; END PROCESS; END;
四 mux程序 LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL; ENTITY mux IS
PORT (A,B,S,START:IN STD_LOGIC; Y:OUT STD_LOGIC); END ENTITY mux;
ARCHITECTURE one OF mux IS BEGIN
PROCESS(START,A,B,S) BEGIN
IF START<='0' THEN Y<='0'; ELSIF S<='0' THEN Y<=A; ELSE Y<=B;
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现代电子系统设计课程设计说明书
END IF; END PROCESS; END;
五 fenpinqi程序 Library ieee;
Use ieee.std_logic_unsigned.all; Use ieee.std_logic_1164.all; Entity fenpinqi is
Port ( clkk: in std_logic; cnt_en: out std_logic; load: out std_logic; rst_cnt: out std_logic); end fenpinqi;
architecture behav of fenpinqi is signal div2clk :std_logic; begin
process(clkk) begin
if clkk'event and clkk='1' then div2clk<=not div2clk; end if; end process;
process(clkk,div2clk) begin
if clkk='0' and div2clk='0' then rst_cnt<='1'; else rst_cnt<='0'; end if;
end process;
load<=not div2clk; cnt_en<=div2clk; end behav;
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现代电子系统设计课程设计说明书
附录2 系统整体原理图：
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现代电子系统设计课程设计说明书
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