msp430实用程序汇总(5)

2019-03-10 13:34

{

BoardConfig(0xb8);

WDTCTL = WDTPW + WDTHOLD; // Stop watchdog timer

FCTL2 = FWKEY + FSSEL0 + FN0; // MCLK/2 for Flash Timing Generator value = 0; // Initialize value

while(1) // Repeat forever {

write_SegA(value++); // Write segment A, increment value copy_A2B(); _NOP(); } }

void write_SegA (uchar value) {

uchar *Flash_ptr; uint i;

Flash_ptr = (uchar *) 0x1080; FCTL1 = FWKEY + ERASE; FCTL3 = FWKEY; *Flash_ptr = 0;

FCTL1 = FWKEY + WRT;

for (i=0; i<128; i++) {

*Flash_ptr++ = value; }

FCTL1 = FWKEY; FCTL3 = FWKEY + LOCK; }

void copy_A2B (void) {

uchar *Flash_ptrA; uchar *Flash_ptrB; uint i;

Flash_ptrA = (uchar *) 0x1080; Flash_ptrB = (uchar *) 0x1000; FCTL1 = FWKEY + ERASE;

// Copy segment A to B

// SET BREAKPOINT HERE // Flash pointer // Initialize Flash pointer // Set Erase bit // Clear Lock bit

// Dummy write to erase Flash segment // Set WRT bit for write operation // Write value to flash // Clear WRT bit // Set LOCK bit // Segment A pointer // Segment B pointer // Initialize Flash segment A pointer // Initialize Flash segment B pointer // Set Erase bit

FCTL3 = FWKEY; // Clear Lock bit

*Flash_ptrB = 0; // Dummy write to erase Flash segment B FCTL1 = FWKEY + WRT; // Set WRT bit for write operation

for (i=0; i<128; i++) {

DataBuffer[i] = *Flash_ptrA++;

*Flash_ptrB++ = DataBuffer[i]; // Copy value segment A to segment B }

FCTL1 = FWKEY; // Clear WRT bit FCTL3 = FWKEY + LOCK; // Set LOCK bit }

//****************************************************************************** // MSP-FET430P140 Demo - USART0, Ultra-Low Pwr UART 2400 Echo ISR, 32kHz ACLK //

// Description: Echo a received character, RX ISR used. In the Mainloop UART0 // is made ready to receive one character with interrupt active. The Mainloop // waits in LPM3. The UART0 ISR forces the Mainloop to exit LPM3 after // receiving one character which echo's back the received character.

// ACLK = UCLK0 = LFXT1 = 32768, MCLK = SMCLK = DCO~ 800k

// Baud rate divider with 32768hz XTAL @2400 = 32768Hz/2400 = 13.65 (000Dh) // //* An external watch crystal is required on XIN XOUT for ACLK *// //

// MSP430F149 // -----------------

// /|\\| XIN|-

// | | | 32kHz // --|RST XOUT|- // | |

// | P3.4|-----------> // | | 2400 - 8N1 // | P3.5|<----------- // //

// M. Buccini

// Texas Instruments Inc. // Feb 2005

// Built with IAR Embedded Workbench Version: 3.21A

//******************************************************************************

#include #include \

void main(void) {

BoardConfig(0xb8);

WDTCTL = WDTPW + WDTHOLD; // Stop WDT

P3SEL |= 0x30; // P3.4,5 = USART0 TXD/RXD ME1 |= UTXE0 + URXE0; // Enable USART0 TXD/RXD UCTL0 |= CHAR; // 8-bit character UTCTL0 |= SSEL0; // UCLK = ACLK UBR00 = 0x0D; // 32k/2400 - 13.65 UBR10 = 0x00; //

UMCTL0 = 0x6B; // Modulation

UCTL0 &= ~SWRST; // Initialize USART state machine IE1 |= URXIE0; // Enable USART0 RX interrupt

// Mainloop for (;;) {

_BIS_SR(LPM3_bits + GIE); // Enter LPM3 w/interrupt while (!(IFG1 & UTXIFG0)); // USART0 TX buffer ready? TXBUF0 = RXBUF0; // RXBUF0 to TXBUF0 } }

// UART0 RX ISR will for exit from LPM3 in Mainloop #pragma vector=UART0RX_VECTOR __interrupt void usart0_rx (void) {

_BIC_SR_IRQ(LPM3_bits); // Clear LPM3 bits from 0(SR) }

//****************************************************************************** // MSP-FET430P140 Demo - USART0, Ultra-Low Pwr UART 9600 Echo ISR, 32kHz ACLK //

// ACLK = UCLK0 = LFXT1 = 32768, MCLK = SMCLK = DCO~ 800k

// Baud rate divider with 32768hz XTAL @9600 = 32768Hz/9600 = 3.41 (0003h 4Ah ) // //* An external watch crystal is required on XIN XOUT for ACLK *// //

// MSP430F149 // -----------------

// /|\\| XIN|-

// | | | 32kHz // --|RST XOUT|-

// | |

// | P3.4|-----------> // | | 9600 - 8N1 // | P3.5|<----------- // //

// M. Buccini

// Texas Instruments Inc. // Feb 2005

// Built with IAR Embedded Workbench Version: 3.21A

//******************************************************************************

#include #include \

void main(void) {

BoardConfig(0xb8);

WDTCTL = WDTPW + WDTHOLD; // Stop WDT

P3SEL |= 0x30; // P3.4,5 = USART0 TXD/RXD ME1 |= UTXE0 + URXE0; // Enable USART0 TXD/RXD UCTL0 |= CHAR; // 8-bit character UTCTL0 |= SSEL0; // UCLK = ACLK UBR00 = 0x03; // 32k/9600 - 3.41 UBR10 = 0x00; //

UMCTL0 = 0x4A; // Modulation

UCTL0 &= ~SWRST; // Initialize USART state machine IE1 |= URXIE0; // Enable USART0 RX interrupt

// Mainloop for (;;) {

_BIS_SR(LPM3_bits + GIE); // Enter LPM3 w/interrupt while (!(IFG1 & UTXIFG0)); // USART0 TX buffer ready? TXBUF0 = RXBUF0; // RXBUF0 to TXBUF0 } }

// UART0 RX ISR will for exit from LPM3 in Mainloop #pragma vector=UART0RX_VECTOR __interrupt void usart0_rx (void) {

_BIC_SR_IRQ(LPM3_bits); // Clear LPM3 bits from 0(SR) }

//****************************************************************************** // MSP-FET430P140 Demo - USART0, UART 19200 Echo ISR, XT2 HF XTAL ACLK //

// Description: Echo a received character, RX ISR used. Normal mode is LPM0, // USART0 RX interrupt triggers TX Echo. Though not required, MCLK = XT2. // ACLK = n/a, MCLK = SMCLK = UCLK0 = XT2 = 8MHz

// Baud rate divider with 8Mhz XTAL @19200 = 8MHz/19200 = 416.66 ~ 417 (01A0h) // //* An external 8MHz XTAL on X2IN X2OUT is required for XT2CLK *// // //* Min Vcc required varies with MCLK frequency - refer to datasheet *// // //

// MSP430F149 // -----------------

// /|\\| XT2IN|-

// | | | 8Mhz // --|RST XT2OUT|- // | |

// | P3.4|------------> // | | 19200 - 8N1 // | P3.5|<------------ // //

// M. Buccini

// Texas Instruments Inc. // Feb 2005

// Built with IAR Embedded Workbench Version: 3.21A

//******************************************************************************

#include #include \

void main(void) {

volatile unsigned int i;

BoardConfig(0xb8);

P3SEL |= 0x30; // P3.4,5 = USART0 TXD/RXD WDTCTL = WDTPW + WDTHOLD; // Stop WDT

BCSCTL1 &= ~XT2OFF; // XT2on do {

IFG1 &= ~OFIFG; // Clear OSCFault flag for (i = 0xFF; i > 0; i--); // Time for flag to set

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