of magnitude values. The ROM table is generated by taking all possible phase value addresses and map to a real magnitude sine value rounded to the nearest D bits. Thus, the maximum error output is ±- ? LSB giving a worst case spur of -20log(2D)dBc.
Like the NCO ROM table, a DAC quantizes the digital magnitude values. A DAC, however, outputs an analog voltage corresponding to the digital input value. When designing the NCO sinusoidal ROM table, one should take some empirical data on the DAC linearity to better understand the interaction between the ROM table and the DAC. The quantization for a DAC is specified against an ideal linear plot of digital input versus analog output. Two linearity parameters, differential and integral linearity, are used to specify a DAC’s performance.
Differential linearity is the output step size from bit to bit. A DAC must guarantee a differential linearity of a maximum 1 LSB. When an input code is increased, the DAC output must increase. If the DAC voltage does not increase versus an increase digital input value, the DAC is said to be missing codes. Thus, a 10 bit DAC that has a differential linearity of greater that 1 LSB is only accurate to 9 or less bits. The number of accurate output bits will specify the DDS spurious performance as -20log(2dl) where dl is the number differential linear bits..
Integral linearity is a measure of the DAC’s overall linear performance versus an ideal linear straight line. The straight line plot can be either a “best straight line” where DC offsets are possible at both the min and max outputs of the DAC, or the straight line can cross the end points of the min and max output values. A DAC will tend to have a characteristic curve that is traversed over the output range. Depending on the shape and symmetry (symmetry about the half way point of the DAC output) of this curve, output harmonics of the DDS fundamental output frequency will be produced. As these harmonics approach and cross the Nyquist frequency of Fclk/2, the harmonics become under sampled and reflect back into the band of interest, 0 to Fclk/2. This problem is best illustrated by setting the NCO output to Fclk/4 plus a slight offset. The third harmonic will fall minus 3 folds the small offset from the fundamental and the second harmonic will cross the Nyquist frequency by 2 folds the small offset leaving a reflected image back in the band of interest A sample plot of this frequency setup is shown in Figure 5.
Other DAC characteristic that will produce harmonic distortion is any disruption of the symmetry of the output wave form such as a different rise and fall time. These characteristics can typically be corrected by board components external to the DAC such as an RF transformer, board layout issues, attenuation pads etc.
Given the complexities of the DDS system, engineers should consider implementing
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the design using separate devices for the numerically controlled oscillator, the digital to analog converter, and the low pass filter. This approach allows for signal observation at many points in the system, yet is compact enough to be practical as an end-solution. Alternatively, the discrete implementation can serve as a prototyping vehicle for a single-chip mixed signal ASIC.
The author developed a version of the design using a Harris HI5721 evaluation board for the DAC. The NCO at the heart of the DDS design, and a random generator to test signal modulation, was implemented into about 65% of a QuickLogic field programmable gate array (FPGA). This FPGA, a QL16x24B 4000-gate device, was chosen for its high performance, ease-of-use, and powerful development tools. The NCO design included following:
Developed in Verilog with the 8 bit CLA adder schematic captured and net listed to Verilog 32 bit frequency word input
32 phase accumulator pipelined over 8 bits 8 bit phase moudulation word input 8 bit sine ROM look-up table
The design was described mostly in Verilog, with an 8 bit carry look ahead adder modified from QuickLogic’s macro library netlisted to Verilog. The whole design cycle was less than four days (two days to describe the design and a day and a half to prototype the hardware). Everything worked perfectly the first time, with the design running at an impressive 45MHz as predicted by the software simulation tools.
Plots used in the article to illustrate DDS performance parameters were provided from the test configuration.
Figure 6 below shows the external IO interface to the NCO design .The function of each signal is described in the following table.
Signal Function Table FREQWORD[31:0] PHASEWORD[7:0] This input is the frequency control word to the NCO. This word controls the phase accumulator rate, and thus, the output frequency of the DACOUT sinusoidal wave form. The output carrier frequency is calculated by the following : This input is the phase modulation control word to the NCO. This word controls the phase offset following the phase accumulator. This phase offset is used to phase modulate the output carrier. 31
FWWRN This input is the low asserted frequency word write strobe. This strobe input registers the FREQWORD input on the rising edge. This strobe can be asynchronous to the SYSCLK. SYSCLK This is the reference system clock input to the NCO. This clock is the sampling clock of the output carrier. PNCLK This input is the pseudo-noise generator clock input. This clock sets the data rate of the I and Q data outputs. RESETN This input is a low asserted global reset. When asserted, the internal phase and frequency word registers are cleared stopping the output carrier at 0 radians. DACOUT[7:0] This output is the sinusoidal DAC amplitude word. This word is valid on the rising edge of the DACCLK. The sinusoidal wave form output is represented by the following : f(t) = sin(2pFout(t) + Pout) DACCLK This output is the DAC clock strobe. This clock is the SYSCLK feed back to an output pin compensating for the latency of the NCO IO pins. The DACOUT amplitude words will be valid on the rising edge of the DACCLK. SIN This output is a single bit digital sine wave output. This sine wave output comes from the MSB of the phase accumulator. The output frequency of this pin is controlled by the frequency word input. COS This output is a single bit digital cosine wave output. This cosine wave output comes form the MSB and next most significant bit of the phase accumulator. The output frequency of this pin is controlled by the frequency word input. MSIN This output is a single bit digital sine wave output. This sine wave output comes from the MSB of the phase modulator. The output frequency of this pin is controlled by the frequency word input and phase offset bythe phase word input. This sine wave output is the same as the SIN output with a phase offset of plus 2p/28 * PHASEWORD. MCOS This output is a single bit digital cosine wave output. This cosine wave output comes form the MSB and next most significant bit of the phase modulator. The output frequency of this pin is controlled by the frequency word input and the phase offset by the phase word input. This cosine 32
wave outputis the same as the COS output with a phase offset of plus 2p/28 * PHASEWORD. IDATA QDATA This output is a 25 - 1 pseudo noise random pattern. This output is not a functional part of the NCO design but used to demonstrate phasemodulation using the phase port. This output is a 25 - 1 pseudo noise random pattern. This output is not a functional part of the NCO design but used to demonstrate phase modulation using the phase port. Figure 6: The External IO Interface Top Level (dds.v)
The top level of the NCO design instantiates the functional blocks of the NCO design and the PN generator block.
PN Generator (pngen.v)
This module is not part of the NCO design but is used to produce a sample random data pattern to modulate the carrier output. This module uses the PNCLK input to clock two Gold code 5 bit PN generators. The outputs of the PN generators are IDATA and QDATA outputs.
The lower level block of this NCO design consist of a synchronous frequency word input register, a synchronous phase word input register, a 32 bit pipe lined phase accumulator, an 8 bit phase adder, and a sin lockup table. A detailed description of each of the NCO blocks and the PN generator are provided in the following sections.
Load Frequency Word (loadfw.v)
The load frequency word block is a synchronizing loading circuit. The FREQWORD[31:0] input drives a the data input to the 32 bit fwreg register that is sampled on the rising edge of the FWWRN write strobe. The FWWRN strobe also drives the data input to a metastable flip flop fwwrnm that is used in conjunction with a synchronous register fwwrns to produce a FWWRN rising edge strobe. This rising edge strobe loadp1 is then piped for an additional 3 clock cycles producing the load strobes loadp2, loadp3, and loadp4. The load strobes are used to signal when to update the synchronous pipe line 8 bit registers pipefw1, pipefw2, pipefw3, and pipefw4 to the sampled frequency word content. The pipe line registers are concatenated to produce the 32 bit synchronous frequency word output SYNCFREQ[31:0] that is staggered to compensate for the 32 bit pipe lined phase adder.
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Phase Word Accumulator (phasea.v)
The phase accumulator block is a 32 bit accumulator that is pipe lined in 8 bit sections. This module instanciates a schematic captured carry lock ahead CLA adder that has a carry in and carry out port. The synchronous frequency word, staggered to match the pipe lined accumulator, is loaded into the B input of the CLA adders. The sum output of the CLA adders are registered in the pipe registered with the output tied back to the A input of the CLA adders. The carry output of the CLA adders is registered in the pipec registers with the output tied to the next most significant CLA adder carry input. The most significant sum output register pipe4 is assigned to the PHASE output port giving a phase value quantized to 8 bits. A digital sine and cosine value is also calculated from the pipe4 register and brought out of the chip as SIN and COS.
Load Phase Word (loadpw.v)
The load phase word block is a synchronizing loading circuit. The PHASEWORD[7:0] input drives the data input to the 32 bit pwreg register that is sampled on the rising edge of the PWWRN write strobe. The PWWRN strobe also drives the data input to a metastable flip flop pwwrnm that is used in conjunction with a synchronous register pwwrns to produce a FWWRN rising edge strobe. This rising edge strobe load is used to signal when to update the synchronous phase word register phswd. The phswd register is assigned to the synchronous phase word output SYNCPHSWD[7:0].
Phase Modulator (phasemod.v)
The phase modulator block is used to phase offset the phase accumulator 8 bit quantized output with the synchronous phase word from the load phase word block. This module instantiates a CLA adder with the A input tied to the synchronous phase output and the B input tied to the phase accumulator output. The sum output of the adder is registered in the mphsreg register and assigned to the MODPHASE output port. A modulated version of the sine and cosine values are calculated and brought out of the chip as MSIN and MCOS.
Sine Lockup (sinlup.v)
This module takes the modulated phase value form the phase modulator block and translated the quantized 8 bit value into a sine wave form amplitude value quantized to 8 bits. The translation from phase to amplitude is performed by a sine ROM table that in instantiated in this module. The ROM table is reduced to a ? of the symmetrical sine wave form and the MSB of the sine wave form is equivalent to the modulated phase input.This module performs the calculations to reconstruct a complete period of the sine wave form from the ? representation of the ROM table and the MSB of the modulated phase input.
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