elsif(clk'event and clk='1') then
if(cc<9) then
cc<=cc+1;
else
cc<=0;
end if;
if cc=9 then tmp<=tmp xor \end if;
end if;
Q<=tmp; end process; end architecture s;
-------------波形选择------------------------------------------------------------------------------------------ library ieee;
use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity chs is
port(ob,si,dl,sq: in std_logic;
obl,sin,dlt,squ: in std_logic_vector(7 downto 0);
Q:out std_logic_vector(7 downto 0)); end entity chs; architecture ch of chs is
signal tmp: std_logic_vector(3 downto 0); signal tt:std_logic_vector(9 downto 0); begin
process(ob,si,dl,sq)is begin
tmp<=ob&si&dl&sq; case tmp is
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when \when \when \when \
when \when \when \ when \when \when \when others=>null;
end case; end process; end architecture ch;
------------调度程序-------------------------------------------------------------------------------------------- --------------开始------------------------------------------------------------------------------------------------ library ieee;
use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all;
--------------------------------------------------------------------------------------------------------------------- entity s_gen is
port(clk ,reset: in std_logic;
ob,si,dl,sq: in std_logic;
tc: in std_logic_vector(1 downto 0); a,b,c,d,e,f,g:out std_logic;
wr:out std_logic;
Q:out std_logic_vector(7 downto 0)); end entity s_gen;
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--------------------------------------------------------------------------------------------------------------------- architecture behav of s_gen is
--------元件定义------------------------------------------------------------------------------------------------- component obl is port(clk,reset:in std_logic;
Q:out std_logic_vector(7 downto 0));
end component obl; component sin is port(clk,reset:in std_logic;
Q:out std_logic_vector(7 downto 0));
end component sin; component dlt is port(clk,reset:in std_logic;
Q:out std_logic_vector(7 downto 0));
end component dlt; component squ is port(clk,reset:in std_logic;
Q:out std_logic_vector(7 downto 0));
end component squ; component chs is
port(ob,si,dl,sq: in std_logic;
obl,sin,dlt,squ: in std_logic_vector(7 downto 0);
Q:out std_logic_vector(7 downto 0)); end component chs;
----------信号定义----------------------------------------------------------------------------------------------- signal J,K,L,Z: std_logic_vector(7 downto 0); signal JJ,KK,LL,ZZ: std_logic_vector(7 downto 0); signal s: std_logic_vector(6 downto 0); begin
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----------启动DAC0832--------------------------------------------------------------------------------------- process(clk)is begin
if(clk'event and clk='1') then
if(reset='1') then wr<='1'; else wr<='0'; end if;
end if; end process;
----------信号衰减选择----------------------------------------------------------------------------------------- process(tc,J,K,L,Z)is begin case tc is
when \
when \
LL<='0'&L(7 downto 1);ZZ<='0'&Z(7 downto 1);
when \
LL<=\
when \
LL<=\
when others=>null; end case;
if tc=\elsif tc=\elsif tc=\elsif tc=\end if;
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a<=s(6);b<=s(5);c<=s(4);d<=s(3);e<=s(2);f<=s(1);g<=s(0); end process;
---------元件例化------------------------------------------------------------------------------------------------ u0: obl port map(clk,reset,J); u1: sin port map(clk,reset,K); u2: dlt port map(clk,reset,L); u3: squ port map(clk,reset,Z);
u4: chs port map(ob,si,dl,sq,JJ,KK,LL,ZZ,Q);
--------------------------------------------------------------------------------------------------------------------- end architecture behav;
-----------结束---------------------------------------------------------------------------------------------------- ---------------------------------------------------------------------------------------------------------------------
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