);
reset_ibuf_9 : X_BUF port map ( I => reset, O => reset_ibuf );
q_7_ibuf_10 : X_BUF port map ( I => q(7), O => q_7_ibuf );
q_6_ibuf_11 : X_BUF port map ( I => q(6), O => q_6_ibuf );
q_5_ibuf_12 : X_BUF port map ( I => q(5), O => q_5_ibuf );
q_4_ibuf_13 : X_BUF port map ( I => q(4), O => q_4_ibuf );
q_3_ibuf_14 : X_BUF port map ( I => q(3), O => q_3_ibuf );
q_2_ibuf_15 : X_BUF port map ( I => q(2), O => q_2_ibuf );
q_1_ibuf_16 : X_BUF port map ( I => q(1), O => q_1_ibuf );
q_0_ibuf_17 : X_BUF port map ( I => q(0),
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O => q_0_ibuf );
v1_3_obuf : X_BUF port map ( I => v2_0_obuf, O => v1_3_obuf_GTS_TRI );
v1_2_obuf : X_BUF port map ( I => v2_0_obuf, O => v1_2_obuf_GTS_TRI );
v1_1_obuf : X_BUF port map ( I => v2_0_obuf, O => v1_1_obuf_GTS_TRI );
v1_0_obuf : X_BUF port map ( I => v2_0_obuf, O => v1_0_obuf_GTS_TRI );
v2_3_obuf : X_BUF port map ( I => v2_0_obuf, O => v2_3_obuf_GTS_TRI );
v2_2_obuf : X_BUF port map ( I => v2_0_obuf, O => v2_2_obuf_GTS_TRI );
v2_1_obuf : X_BUF port map ( I => v2_0_obuf, O => v2_1_obuf_GTS_TRI );
v2_0_obuf_18 : X_BUF port map ( I => v2_0_obuf, O => v2_0_obuf_GTS_TRI );
v3_3_obuf : X_BUF port map (
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I => v33(3),
O => v3_3_obuf_GTS_TRI );
v3_2_obuf : X_BUF port map ( I => v33(2),
O => v3_2_obuf_GTS_TRI );
v3_1_obuf : X_BUF port map ( I => v33(1),
O => v3_1_obuf_GTS_TRI );
v3_0_obuf : X_BUF port map ( I => v33(0),
O => v3_0_obuf_GTS_TRI );
v4_3_obuf : X_BUF port map ( I => v44(3),
O => v4_3_obuf_GTS_TRI );
v4_2_obuf : X_BUF port map ( I => v44(2),
O => v4_2_obuf_GTS_TRI );
v4_1_obuf : X_BUF port map ( I => v44(1),
O => v4_1_obuf_GTS_TRI );
v4_0_obuf : X_BUF port map ( I => v44(0),
O => v4_0_obuf_GTS_TRI );
v5_3_obuf : X_BUF port map ( I => v55(3),
O => v5_3_obuf_GTS_TRI );
v33_madd_n0000_inst_lut2_01 : X_LUT2
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generic map( INIT => X\ )
port map ( ADR0 => v33(0), ADR1 => GND,
O => v33_madd_n0000_inst_lut2_01_O );
v33_madd_n0000_inst_lut2_01_LUT1_L_BUF : X_BUF port map (
I => v33_madd_n0000_inst_lut2_01_O, O => v33_madd_n0000_inst_lut2_0 );
v55_madd_n0000_inst_lut2_01 : X_LUT2 generic map( INIT => X\ )
port map ( ADR0 => v55(0), ADR1 => GND,
O => v55_madd_n0000_inst_lut2_01_O );
v55_madd_n0000_inst_lut2_01_LUT1_L_BUF : X_BUF port map (
I => v55_madd_n0000_inst_lut2_01_O, O => v55_madd_n0000_inst_lut2_0 );
v44_madd_n0000_inst_lut2_01 : X_LUT2 generic map( INIT => X\ )
port map ( ADR0 => v44(0), ADR1 => GND,
O => v44_madd_n0000_inst_lut2_01_O );
v44_madd_n0000_inst_lut2_01_LUT1_L_BUF : X_BUF port map (
I => v44_madd_n0000_inst_lut2_01_O, O => v44_madd_n0000_inst_lut2_0 );
v33_2_rt_21 : X_LUT2 generic map( INIT => X\
39
)
port map ( ADR0 => v33(2), ADR1 => GND, O => v33_2_rt_O );
v33_2_rt_LUT1_L_BUF : X_BUF port map (
I => v33_2_rt_O, O => v33_2_rt );
v33_1_rt_22 : X_LUT2 generic map( INIT => X\ )
port map ( ADR0 => v33(1), ADR1 => GND, O => v33_1_rt_O );
v33_1_rt_LUT1_L_BUF : X_BUF port map (
I => v33_1_rt_O, O => v33_1_rt );
v55_2_rt_23 : X_LUT2 generic map( INIT => X\ )
port map ( ADR0 => v55(2), ADR1 => GND, O => v55_2_rt_O );
v55_2_rt_LUT1_L_BUF : X_BUF port map (
I => v55_2_rt_O, O => v55_2_rt );
v55_1_rt_24 : X_LUT2 generic map( INIT => X\ )
port map (
40