集成电路与verilog语言实验报告
.f(f) );
initial begin
// Initialize Inputs a = 0; b = 0; sel = 0;
// Wait 100 ns for global reset to finish #10;
// Add stimulus here a=1; b=0; sel=0; #10; a=1; b=0; sel=1; #10;
#10$finish; end endmodule
仿真结果：
实验2题目：实现一个计数器，计数时计数器可从0计到10。
源代码：
module counter(din,up1_down0,clk,nrst,sta1_pau0,load,counter); input[3:0] din; input up1_down0; input clk; input nrst;
input sta1_pau0; input load;
output [3:0] counter; reg [3:0] counter; always @(posedge clk or negedge nrst) begin
if(~nrst)
counter <= 4'b0000; else if(load) counter <= din; else begin if(~sta1_pau0) counter <= counter;
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集成电路与verilog语言实验报告
else if(up1_down0) if (counter == 10) counter <= 4'b0000; else counter <= counter + 1; else if (counter == 0) counter <= 4'b1010; else counter <= counter - 1; end end
endmodule
综合结果：
TB代码： module tb2; // Inputs
reg [3:0] din; reg up1_down0; reg clk; reg nrst;
reg sta1_pau0; reg load; // Outputs
wire [3:0] counter;
// Instantiate the Unit Under Test (UUT) counter uut ( .din(din),
.up1_down0(up1_down0), .clk(clk), .nrst(nrst),
.sta1_pau0(sta1_pau0), .load(load), .counter(counter)
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集成电路与verilog语言实验报告
); initial
clk = 1'b0; always
#5 clk = ~clk; initial begin
// Initialize Inputs din = 0;
up1_down0 = 0; nrst = 0; sta1_pau0 = 0; load = 0;
// Wait 100 ns for global reset to finish #50;
// Add stimulus here //从0开始加计数 din = 4'b0111; nrst = 1; up1_down0 = 1; sta1_pau0 = 1; #210; //暂停
sta1_pau0 = 0; #20;
//从7开始减计数 load = 1; #10;
load = 0; sta1_pau0 = 1;
up1_down0 = 0; #200;
#20 $finish; end
endmodule
仿真结果：
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集成电路与verilog语言实验报告
实验3题目：由Morre状态机设计一个简单的交通灯，假定红灯时间为9个时间单位，绿灯时间为6个时间单位，黄灯时间为3个时间单位。
源代码：
module light_machine(clk,nrst,y,t); input clk; input nrst; output [1:0] y; output [3:0] t; reg [3:0] q; reg [1:0] y; reg [1:0] state; reg [3:0] t;
parameter green = 2'b00,yellow = 2'b01,red = 2'b11;
initial begin
q <= 4'b0; t <= 4'b0; end
always @(posedge clk or negedge nrst) begin
if(!nrst) begin
state <= green; y <= 2'bz; end else
case(state) green: begin q <= q +1; t <= q; if(q == 5) begin q <= 4'b0; state <= yellow; end else begin y <= 2'b00; state <= green; end end
yellow: begin q <= q +1; t <= q; if (q == 2) begin q <= 4'b0; state <= red; end else
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集成电路与verilog语言实验报告
begin y <= 2'b01; state <= yellow; end end
red:
begin
q <= q + 1; t <= q; if (q == 8) begin q <= 4'b0; state <= green; end else
begin y <= 2'b11; state <= red; end end endcase end
endmodule
综合结果：
TB代码： module tb_2; // Inputs reg clk; reg nrst; // Outputs wire [1:0] y; wire [3:0] t; // Instantiate the Unit Under Test (UUT) light_machine uut ( .clk(clk), .nrst(nrst), .y(y), .t(t)
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