使用if_then语句来描述四选一数据选择器 library ieee;
use ieee.std_logic_1164.all; entity ze is
port(s0,s1 : in std_logic; a,b,c,d : in std_logic; y:out std_logic); end ze;
architecture ab of ze is
signal s: std_logic_vector(1 downto 0); begin
s<=s1&s0; process(s) begin
if s<=\elsif s<=\elsif s<=\else y<=d; end if;
end process; end ab;
使用case语句来描述四选一数据选择器 library ieee;
use ieee.std_logic_1164.all; entity xuan is
port(s0,s1 : in std_logic; a,b,c,d : in std_logic; y:out std_logic); end xuan;
architecture ab of xuan is
signal s: std_logic_vector(1 downto 0); begin
s<=s1&s0; process(s) begin case s is
when \ when \ when \ when \ when others=>null; end case; end process; end ab;
使用when_else语句来描述四选一数据选择器
library ieee;
use ieee.std_logic_1164.all; entity xuan is
port(s0,s1 : in std_logic; a,b,c,d : in std_logic; y:out std_logic); end xuan;
architecture ab of xuan is
signal s: std_logic_vector(1 downto 0); begin
s<=s1&s0;
y<=a when s<=\ b when s<=\
c when s<=\ d ;
end ab;