IF /request_in == GND # /local_request == GND THEN /request_out = GND;
END IF;
IF /grant_in == GND THEN IF /local_request == GND THEN /local_grant = GND; ELSIF /request_in == GND THEN
/grant_out = GND;
END IF;
END IF;
END;
(4) 时序逻辑
例1：定义D触发器的输入输出信号。 SUBDESIGN bur_reg (
clk, load, d[7..0] : INPUT; q[7..0] : OUTPUT; )
VARIABLE
ff[7..0] : DFFE; BEGIN ff[].clk = clk; ff[].ena = load; ff[].d = d[]; q[] = ff[].q; END;
该例中分别定义7个D触发器的信号
例2：调用巨功能模块 INCLUDE \SUBDESIGN lpm_reg (
clk, load, d[7..0] : INPUT; q[7..0] : OUTPUT;
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) BEGIN
q[] = lpm_dff (.clock=clk, .enable=load, .data[]=d[]) WITH (LPM_WIDTH=8) RETURNS (.q[]); END;
例3：在变量段声明寄存器的输出。 SUBDESIGN reg_out (
clk, load, d[7..0] : INPUT; q[7..0] : OUTPUT; )
VARIABLE
q[7..0] : DFFE; % outputs also declared as registers % BEGIN q[].clk = clk; q[].ena = load; q[] = d[]; END;
例4：16位计数器例 SUBDESIGN ahdlcnt (
clk, load, ena, clr, d[15..0] : INPUT; q[15..0] : OUTPUT; )
VARIABLE
count[15..0] : DFF; BEGIN
count[].clk = clk;
count[].clrn = !clr; %清零% IF load THEN
count[].d = d[]; %置数% ELSIF ena THEN
count[].d = count[].q + 1; %计数%
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ELSE
count[].d = count[].q; %保持% END IF; q[] = count[]; END;
例5：具有D触发器功能的状态机 SUBDESIGN simple (
clk, reset, d : INPUT; q : OUTPUT; )
VARIABLE
ss: MACHINE WITH STATES (s0, s1); BEGIN ss.clk = clk; ss.reset = reset; CASE ss IS WHEN s0 => q = GND; IF d THEN ss = s1; END IF; WHEN s1 => q = VCC; IF !d THEN ss = s0; END IF; END CASE; END;
例6：步进马达控制器 SUBDESIGN stepper (
clk, reset : INPUT;
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ccw, cw : INPUT; phase[3..0] : OUTPUT; )
VARIABLE
ss: MACHINE OF BITS (phase[3..0]) WITH STATES ( s0 = B\ s1 = B\ s2 = B\ s3 = B\BEGIN
ss.clk = clk; ss.reset = reset; TABLE
ss, ccw, cw => ss; %--------------------------------------------------% s0, 1, x => s3; s0, x, 1 => s1; s1, 1, x => s0; s1, x, 1 => s2; s2, 1, x => s1; s2, x, 1 => s3; s3, 1, x => s2; s3, x, 1 => s0; END TABLE; END;
例7：指定一个输出BIT的状态机 SUBDESIGN moore1 (
clk : INPUT; reset : INPUT; y : INPUT; z : OUTPUT; )
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VARIABLE
% current current % % state output % ss: MACHINE OF BITS (z) WITH STATES (s0 = 0, s1 = 1, s2 = 1, s3 = 0); BEGIN
ss.clk = clk; ss.reset = reset; TABLE
% current current next % % state input state % ss, y => ss; %-------------------------------------% s0, 0 => s0; s0, 1 => s2; s1, 0 => s0; s1, 1 => s2; s2, 0 => s2; s2, 1 => s3; s3, 0 => s3; s3, 1 => s1; END TABLE; END;
例8：不声明输出状态的状态机 SUBDESIGN moore2 (
clk : INPUT; reset : INPUT; y : INPUT; z : OUTPUT; )
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